This letter presents a spin-orbit torque magnetic random access memory (SOT-MRAM) for high-density, reliable, and energy-efficient on-chip memory application. Unlike the conventional SOT-MRAM requiring two access transistors, the proposed MRAM uses only one access transistor along with a Schottky diode in order to achieve high integration density while maintaining the advantages of SOT-MRAM, such as low write energy and enhanced reliability of magnetic tunnel junction. The Schottky diode is forward-biased during read, whereas it is reverse-biased during write to prevent sneak current paths. Our simulation results show that the proposed MRAM can achieve 30% and 50% reduction in bit-cell area in comparison to conventional spin-transfer torque MRAM (STT-MRAM) and SOT-MRAM, respectively, and ~2.5× improvement in write power compared with the STT-MRAM.

This brief proposes a new design technique for spin-orbit torque magnetic random access memory (SOT-MRAM), suitable for high-density and low-power on-chip cache applications. A bitline of the proposed memory bit cell is shared with that of an adjacent bit cell leading to a reduction in the number of metals along the column direction. This results in higher integration density due to improved metal pitch limited region. The proposed memory can optimize the bit-cell area by aggressively reducing the size of write access transistor, since SOT-based switching operation of SOT devices translates to smaller size of write access transistor. Furthermore, the proposed SOT-MRAM still retains the advantages of SOT-MRAM such as low write energy dissipation, high read-disturb margin, and improved reliability of magnetic tunnel junction. In comparison with the conventional SOT-MRAM bit cells, our proposed MRAM bit cell can have 20% less bit-cell area. Even compared with the standard STT-MRAM, our proposed bit cell still achieves higher integration density. Moreover, the shared bitline SOT-MRAM achieves >6× lower write power and higher read-disturb margin than does the STT-MRAM.

This paper proposes two types of dual-ported (1-read/1-write: 1R/1W) spin-Hall magnetic random-access memory (SH-MRAM) suitable for on-chip cache applications. Separate write and read ports allow simultaneous write and read access, which can mitigate the impact of slow write latency on the system performance without any area overhead compared to the single-ported SH-MRAM. The efficient spin-Hall effect based spin-transfer torque (STT) leads to low-power write operation. In addition, separate read and write current paths of the devices can enhance the read operation without much impact on the write operation. The differential sensing scheme in 1R/1W differential SH-MRAM can further improve sensing power and sensing margin. Compared to the 1R/1W STT-MRAM bit cell, the 1R/1W SH-MRAM bit cell can achieve lower power consumption for write operation and higher sensing margin with low read power consumption under an iso-area condition.

This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to high-density memory implementation because of the use of two access transistors per cell. We first analyze the layout of the conventional SOT-MRAM bit-cell that includes two vertical metal lines, a bit-line and a source-line, limiting the horizontal dimension. We further propose two design techniques to reduce the horizontal dimension by decreasing the number of metal lines per cell without any performance overhead. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, the proposed techniques share a single source-line between two consecutive bit-cells in the same row. The simulation result shows that proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.

Emerging device based spiking neural network (SNN) hardware design has been actively studied. Especially, energy and area efficient synapse crossbar has been of particular interest, but processing units for weight summations in synapse crossbar are still a main bottleneck for energy and area efficient hardware design. In this paper, we propose an efficient SNN architecture with stochastic spin-orbit torque (SOT) device based multi-bit synapses. First, we present SOT device based synapse array using modified gray code. The modified gray code based synapse needs only N devices to represent 2^N levels of synapse weights. Accumulative spike technique is also adopted in the proposed synapse array, to improve ADC utilization and reduce the number of neuron updates. In addition, we propose hardware friendly algorithmic techniques to improve classification accuracies as well as energy efficiencies. Non-spike depression based stochastic spike-timing-dependent plasticity is used to reduce the overlapping input representation and classification error. Early read termination is also employed to reduce energy consumption by turning off less associated neurons. The proposed SNN processor has been implemented using 65nm CMOS process, and it shows 90% classification accuracy in MNIST dataset consuming 0.78J/image (training) and 0.23J/image (inference) of energy with an area of 1.12mm2.

Nonvolatile flip-flop (NVFF) using spin-transfer torque magnetic tunnel junctions (STT-MTJs) has been proposed to enable line-grain power gating systems. However, the STT-MTJ-based NVFF (STT-NVFF) may not perform fast backup and disturb-free restore operations. We propose a new NVFF using complementary polarizer MTJ (CPMTJ) to alleviate these limitations. Our proposed NVFF exploits the CPMTJ structure for fast- and low-energy backup operation. The estimated backup delay is less than 10 ns in 7-nm node FinFET technology with CPMTJ size of 12 nm × 33 nm in a rectangular shape. Furthermore, during the restore operation, CPMTJ provides guaranteed disturb-free sensing, since the disturb torque from the two complementary pinned layers of CPMTJ cancels each other. The simulation results show 2 times improvement in the backup delay with higher restore-disturb margin compared with STT-NVFF.