As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, through silicon vias (TSV) and wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 10 mm-2. In this article, the reliability challenges and failure mechanisms related to these two technologies are reviewed and potential mitigation solutions developed at imec are introduced. In the first section, the process and technology choices enabling the TSV and SiCN–SiCN wafer-to-wafer hybrid-bonding technologies are summarized. Subsequently, the impact of mechanical stress and liner integrity on the reliability of TSVs are discussed. In this context, it is shown that copper poisoning in the dielectric during the liner opening etch is a major challenge, requiring careful optimization of the etch recipe. A lifetime assessment of the hybrid-bonding pad-to-pad interface is then presented. The importance of a soft CMP process, that minimizes the degradation of the bonding dielectric and therefore the creation of defects is demonstrated. Additionally, the impact of copper migration along the bonding interface on the reliability performance is mentioned. Finally, the role of bonding voids in the electromigration performances of copper pads will be discussed.

Reliability results obtained on a photosensitive polymer-based RDL process with two-metal layers and a target pitch below 4 μm are presented. Fully processed samples have been subjected to 1000 hours of high temperature storage performed at 150 °C when a second set of samples endured a temperature-humidity stress executed at 85 °C and 85 %RH. A thermal cycling stress between -50 °C and 125 °C for 1000 cycles was also performed on a third sample set. After 1000 hours spent at 150 °C, an increase in the metal line resistivity resulting from copper oxidation by atmospheric oxygen diffusing through the polymer is observed. The oxidation of the top part of the metal lines is further confirmed by failure analyses performed on the stressed samples. Eight different polymers used as a potential capping solution to block the diffusion of oxygen toward the metal lines are investigated. The most promising approach for a reliable polymer-based RDL process involves the use of a mold layer.

In this article, the reliability assessment of a 2.5-D metal–insulator–metal (MIM) capacitor, built in a thicker back-end of line layer using a 23-nm-thick ALD-deposited Al-doped HfO2 high- $\kappa $ dielectric, is performed using time-dependent dielectric breakdown (TDDB) measurements. This capacitor, compatible with back-side power delivery network (PDN) technologies, presents a density above 16.7 nF/mm2 while retaining a leakage current lower than 0.3 pA/nF at 2 V and 100 °C. It offers a quadratic voltage coefficient of capacitance around 500 ppm/ $\text{V}^{{2}}$ at 25 °C and a temperature coefficient of capacitance of 191 ppm/°C. The breakdown field of this high- $\kappa $ dielectric is around 6.2 MV/cm at 25 °C. The thermochemical formalism commonly used to describe dielectric breakdown was unsuccessfully tested on this device, confirming the joint contribution of current and field in the degradation process. In addition, the time to failure (TTF) temperature dependence is found to follow an Arrhenius mechanism. Assuming a power law (PL) extrapolation model, 800-mm2 capacitors are expected to survive ten years with a failure rate lower than 1 ppm when operated at 100 °C using voltages below or equal to 2.22 V.