Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

Reliability results obtained on a photosensitive polymer-based RDL process with two-metal layers and a target pitch below 4 μm are presented. Fully processed samples have been subjected to 1000 hours of high temperature storage performed at 150 °C when a second set of samples endured a temperature-humidity stress executed at 85 °C and 85 %RH. A thermal cycling stress between -50 °C and 125 °C for 1000 cycles was also performed on a third sample set. After 1000 hours spent at 150 °C, an increase in the metal line resistivity resulting from copper oxidation by atmospheric oxygen diffusing through the polymer is observed. The oxidation of the top part of the metal lines is further confirmed by failure analyses performed on the stressed samples. Eight different polymers used as a potential capping solution to block the diffusion of oxygen toward the metal lines are investigated. The most promising approach for a reliable polymer-based RDL process involves the use of a mold layer.

The field and temperature dependence of the leakage current of low-k material is studied by using planar capacitors. First it is shown that our planar capacitors are suitable test vehicles to analyze the intrinsic properties of low-k materials. Then an evaluation of the trap density of the investigated low-k material is performed. Eventually different models such as Poole-Frenkel emission, Schottky emission and trap-assisted Fowler-Nordheim tunneling are analyzed in a temperature range from 80 K to 473 K and in a field range from 4.2 MV/cm to 6.6 MV/cm. It is found that Poole-Frenkel emission and Schottky emission do not fit the experimental data, whereas trap-assisted Fowler-Nordheim tunneling exhibits an adequate match between the extracted parameters and the theoretical predictions.

The stress of Cu/low-$k$ interconnects with linewidths scaled to 50 nm was determined using precision lattice parameter measurement at an advanced light facility. Grazing incidence and $\theta \text{-}2\theta$ diffraction geometries were used to gain a direct measurement of the strain tensor, showing an increase in stress as the linewidth is reduced an order of magnitude from 500 to 50 nm. This increase in stress contrasts existing predictions of finite element simulations, which predict a decrease in stress as the line aspect ratio increases above one. Our simulations, considering the low-$k$ stack, have shown this decrease should occur at lower aspect ratios; however, neither trend is reflected in the measured data. All of the lines showed a strong [111] texture suggesting their stiffness was not affected at the scaled dimensions. The narrower lines show a more bamboolike structure compared to a more polycrystalline structure in the wider lines. In the narrow lines, the grains become pinned in the linewidth reducing stress relaxation through grain growth or reorder. This leads to the observed increase in stress with linewidth scaling and the increase in stress for bamboo lines during fabrication. This work demonstrates the grain structure of interconnects has a significant effect on stress and stress evolution.

A comprehensive physics-based modeling framework for electromigration (EM) in copper nano-interconnects is presented. It combines the three stages of stress evolution, void nucleation, and void dynamics in a single fully coupled and consolidated platform. Mechanical stress evolution, pre- and post-void nucleation, and its impact on void dynamics are deciphered, which enables accurate predictions of EM aging processes as validated by dedicated EM experiments. Subsequently, the experimentally validated model is utilized to shed light on the impact of a number of manufacturing variables, namely, line extension, via taper angle, and the effectiveness of the via bottom flux divergence point. A linear correlation between the ion leakage through the via bottom barrier and the peak tensile stress at the cathode was observed in long lines. In short lines, a blocked cathode end with atomic leakage through the anode end weakens the back-stress effect and threatens the Blech effect induced interconnect immortality. Increasing the line extension length was shown to increase the EM lifetime by about 40%. This impact was saturated beyond 1 critical dimension of line extension. On the other hand, the via taper angle increased the upstream EM lifetime by about twofold when the taper angle was increased from 0° to 30°, which indicates that the change of via taper angle has a stronger impact on EM lifetime compared to the line extension.