A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.

This paper presents a non-intrusive hybrid fault detection approach that combines hardware and software techniques to detect transient faults in microprocessors. Such faults have a major influence in microprocessor-based systems, affecting both data and control flow. In order to protect the system, an application-oriented hardware module is automatically generated and reconfigured on the system during runtime. When combined with fault tolerance techniques based on software, this solution offers full system protection against transient faults. A fault injection campaign is performed using a MIPS microprocessor executing a set of applications. HW/SW implementation in a reprogrammable platform shows smaller memory area and execution time overhead when compared to related works. Fault injection results show the efficiency of this method by detecting 100% of faults.

This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP3). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed.

Three-dimensional networks on chip (3D-NoCs) have been proposed as an enormously scalable solution to address communication problems in modern systems on chip. Through-silicon via (TSV) is usually adopted as a viable technology enabling vertical connection among NoC layers. However, TSV-based architectures typically exhibit high vulnerability to transient and permanent faults caused by aging effects, thermal violations, manufacturing issues, or even transient fault sources. Therefore, TSV-based architectures call for robust routing schemes capable of sustaining operation under unpredictable failure patterns. In this paper, we introduce FL-RuNS, a fault-tolerant routing scheme for achieving 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. The proposed scheme uses the concept of vertical link announcement to inform nodes in the network of the health condition of vertical links. This mechanism is able to dynamically and progressively reconfigure the entire network without any packet loss. FL-RuNS requires a very low number of asymmetric virtual channels to achieve both deadlock freedom and reachability. Also, FL-RuNS introduces one-flit-dedicated virtual channels, which are used as an escape buffer in case of TSVs failures. The experimental results have confirmed that FL-RuNS shows better reliability when compared to the recently proposed fault-tolerant routing algorithm. Furthermore, the hardware synthesis performed using a commercial 28-nm technology library shows a reasonable area and power overhead with respect to the non-fault-tolerant baseline.

After having carried out radiation experiments on memories, the detected bitflips must be classified into single bit upsets and multiple events to calculate the cross sections of different phenomena. There are some accepted procedures to determine if two bitflips are related. However, if there are enough bitflips, it is possible that unrelated pairs of errors appear in nearby cells and they are erroneously taken as a multiple event. In this paper, radiation experiments are studied as a special case of the urn-and-balls problem in probability theory to estimate how the measured multiple-event cross sections must be corrected to remove the overestimation due to the false events.

In radiation tests on SRAMs or FPGAs, two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests such as the “birthday statistics” have been proposed to estimate the accuracy of the experimental results. In this paper, simple formulae are proposed to determine the expected number of false 2-bit and 3-bit MCUs from the number of bitflips, memory size and the method used to search multiple events. These expressions are validated using Monte Carlo simulations and experimental data. Also, a technique is proposed to refine experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment.