New generation embedded systems demand high performance, efficiency, and flexibility. Reconfigurable hardware can provide all these features. However, the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment, task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on as-soon-as-possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.

A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.

Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP3). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed.

Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section. These tests led to cross-section values two orders of magnitude below those of typical CMOS SRAMs in the same technology node. MUSCA SEP3 simulations complement these results predicting that only high-energy neutrons ( > 30 MeV) can provoke bit flips in the studied SRAMs. MUSCA SEP3 is also used to investigate the sensitivity of the studied SRAM to radioactive contamination and to compare it with the one of standard CMOS SRAMs. Results are useful to make predictions about the operation of this memory in environments such as avionics.