Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >10⁶ cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Resistive random-access memory devices with atomic layer deposition HfO2 and radio frequency sputtering TiOx as resistive switching layers were fabricated successfully. Low-power characteristic with 1.52 μW set power (1 μA@1.52 V) and 1.12 μW reset power (1 μA@1.12 V) was obtained in the HfO2/TiOx resistive random-access memory (RRAM) devices by controlling the oxygen content of the TiOx layer. Besides, the influence of oxygen content during the TiOx sputtering process on the resistive switching properties would be discussed in detail. The investigations indicated that “soft breakdown” occurred easily during the electrical forming/set process in the HfO2/TiOx RRAM devices with high oxygen content of the TiOx layer, resulting in high resistive switching power. Low-power characteristic was obtained in HfO2/TiOx RRAM devices with appropriately high oxygen vacancy density of TiOx layer, suggesting that the appropriate oxygen vacancy density in the TiOx layer could avoid “soft breakdown” through the whole dielectric layers during forming/set process, thus limiting the current flowing through the RRAM device and decreasing operating power consumption.

Reservoir computing is a powerful neural network–based computing paradigm for spatiotemporal signal processing. Recently, physical reservoirs have been explored based on various electronic devices with outstanding efficiency. However, the inflexible temporal dynamics of these reservoirs have posed fundamental restrictions in processing spatiotemporal signals with various timescales. Here, we fabricated thin-film transistors with controllable temporal dynamics, which can be easily tuned with electrical operation signals and showed excellent cycle-to-cycle uniformity. Based on this, we constructed a temporal adaptive reservoir capable of extracting temporal information of multiple timescales, thereby achieving improved accuracy in the human-activity-recognition task. Moreover, by leveraging the former computing output to modify the hyperparameters, we constructed a closed-loop architecture that equips the reservoir computing system with temporal self-adaptability according to the current input. The adaptability is demonstrated by accurate real-time recognition of objects moving at diverse speed levels. This work provides an approach for reservoir computing systems to achieve real-time processing of spatiotemporal signals with compound temporal characteristics.

The exponential growth of various complex images is putting tremendous pressure on storage systems. Here, we propose a memristor-based storage system with an integrated near-storage in-memory computing-based convolutional autoencoder compression network to boost the energy efficiency and speed of the image compression/retrieval and improve the storage density. We adopt the 4-bit memristor arrays to experimentally demonstrate the functions of the system. We propose a step-by-step quantization aware training scheme and an equivalent transformation for transpose convolution to improve the system performance. The system exhibits a high (>33 dB) peak signal-to-noise ratio in the compression and decompression of the ImageNet and Kodak24 datasets. Benchmark comparison results show that the 4-bit memristor-based storage system could reduce the latency and energy consumption by over 20×/5.6× and 180×/91×, respectively, compared with the server-grade central processing unit-based/the graphics processing unit-based processing system, and improve the storage density by more than 3 times.

HfOx-based resistive switching device has been explored as one of the promising candidates for the electronic synapses of neuromorphic computing systems due to its high performance, low cost, and compatibility with CMOS technology. To meet the codesign requirement of HfOx-based electronic synapses with CMOS neurons in the neuromorphic computing systems, a compact model that can capture the synaptic futures of HfOx-based resistive switching device is developed. The developed model can accurately describe the multilevel conductance transition behaviors during RESET process for depression learning as well as the binary stochastic transition behavior during SET process for potentiation learning. After the verification with experimental data, the model is used to simulate a winner-take-all neural network to classify patterns with unsupervised competitive learning algorithm. Simulation results imply that the average recognition accuracy would decrease with the increase of the resistance variation of low resistance state (LRS) due to the “trap” effect. Guided by the simulation, a synapse cell consisted of a HfOX-based device and a fixed resistor series connection is proposed to achieve almost 100% recognition accuracy even if the resistance variation of LRS is 50%.

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and simplify the operation. In the proposed threshold-controlled neuron, no capacitor is utilized, which contributes to higher integration density. The total energy consumption of RRAM synapses for classifying an example is 0.31μJ on average. The proposed system has been implemented on hardware, and has been experimentally demonstrated to show the capability of pattern recognition.