Resistive switching (RS) phenomenon in the HfO₂ dielectric has been indirectly observed at device level in previous studies using metal-insulator-metal structures, but its origin remains unclear. In this work, using the enhanced conductive atomic force microscope (ECAFM), we have been able to obtain in situ direct observation of RS with nanometric resolution. The ECAFM measurements reveal that the conductive filaments exhibiting the RS are primarily formed at the grain boundaries, which were shown exhibiting especially low breakdown voltage due to their intrinsic high density of the oxygen vacancies.

An implantation doping approach is implemented to fabricate Gd-doped ${\text{HfO}}_2$ resistive random access memory (RRAM) devices. The significantly enhanced performances are achieved in the Gd-doped ${\text{HfO}}_2$ RRAM devices including improved uniformity of switching parameters, enlarged ON/OFF ratio, and increased switching speed without obvious reliability degradation. This performance improvement in the Gd-doped ${\text{HfO}}_2$ RRAM devices is clarified to the suppressed randomicity of oxygen vacancy filaments’ formation and the reduced oxygen ion migration barrier induced by trivalent Gd-doping effect. The achieved results also demonstrate the validity of implantation doping approach for the fabrication of RRAM devices.

Resistive random-access memory devices with atomic layer deposition HfO2 and radio frequency sputtering TiOx as resistive switching layers were fabricated successfully. Low-power characteristic with 1.52 μW set power (1 μA@1.52 V) and 1.12 μW reset power (1 μA@1.12 V) was obtained in the HfO2/TiOx resistive random-access memory (RRAM) devices by controlling the oxygen content of the TiOx layer. Besides, the influence of oxygen content during the TiOx sputtering process on the resistive switching properties would be discussed in detail. The investigations indicated that “soft breakdown” occurred easily during the electrical forming/set process in the HfO2/TiOx RRAM devices with high oxygen content of the TiOx layer, resulting in high resistive switching power. Low-power characteristic was obtained in HfO2/TiOx RRAM devices with appropriately high oxygen vacancy density of TiOx layer, suggesting that the appropriate oxygen vacancy density in the TiOx layer could avoid “soft breakdown” through the whole dielectric layers during forming/set process, thus limiting the current flowing through the RRAM device and decreasing operating power consumption.

The exponential growth of various complex images is putting tremendous pressure on storage systems. Here, we propose a memristor-based storage system with an integrated near-storage in-memory computing-based convolutional autoencoder compression network to boost the energy efficiency and speed of the image compression/retrieval and improve the storage density. We adopt the 4-bit memristor arrays to experimentally demonstrate the functions of the system. We propose a step-by-step quantization aware training scheme and an equivalent transformation for transpose convolution to improve the system performance. The system exhibits a high (>33 dB) peak signal-to-noise ratio in the compression and decompression of the ImageNet and Kodak24 datasets. Benchmark comparison results show that the 4-bit memristor-based storage system could reduce the latency and energy consumption by over 20×/5.6× and 180×/91×, respectively, compared with the server-grade central processing unit-based/the graphics processing unit-based processing system, and improve the storage density by more than 3 times.

Nonvolatile and cascadable stateful logic operations are experimentally demonstrated within a 1 k-bit one-transistor-one-resistor (1T1R) resistive random access memory (RRAM) array, where NAND gates serve as the building blocks. A robust dual-gate-voltage operation scheme is proposed. The effects of the transistor ON logic operation and the robustness to device parameter variations are discussed. The parallel 4-bit bitwise XOR operation is experimentally implemented in the 1T1R array by cascading NAND gates. This letter presents a feasible approach to in-memory computing for large-scale circuits.

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and simplify the operation. In the proposed threshold-controlled neuron, no capacitor is utilized, which contributes to higher integration density. The total energy consumption of RRAM synapses for classifying an example is 0.31μJ on average. The proposed system has been implemented on hardware, and has been experimentally demonstrated to show the capability of pattern recognition.