In this paper, we introduce two new 4-moduli sets {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹-1} and {2ⁿ-1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1} for developing efficient large dynamic range (DR) residue number systems (RNS). These moduli sets consist of simple and well-formed moduli which can result in efficient implementation of the reverse converter as well as internal RNS arithmetic circuits. The moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹-1} has 5n-bit DR and it can result in a fast RNS arithmetic unit, while the 6n-bit DR moduli set {2ⁿ-1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1} is a conversion friendly moduli set which can lead to a high-speed and low-cost reverse converter design. Next, efficient reverse converters for the proposed moduli sets based on new Chinese remainder theorems (New CRTs) are presented. The converter for the moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹-1} is derived by New CRT-II with better performance compared to the reverse converter for the latest introduced 5 n-bit DR moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2^n-1-1, 2ⁿ⁺¹-1}. Also, New CRT-I is used to achieve a high-performance reverse converter for the moduli set {2ⁿ-1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1}. This converter has less conversion delay and lower hardware requirements than the reverse converter for a recently suggested 6n-bit DR moduli set {2ⁿ-1, 2ⁿ+1, 2²ⁿ-2, 2²ⁿ⁺¹-3} .

Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field‐effect transistors (CNFETs) can easily be utilised for multiple‐ V _t circuit designs. In this study, a novel energy‐efficient method for designing one‐digit adder is proposed. The suggested design employ ternary multiplexers to select and of input trits for the output node values. This study describes the novel ternary multiplexer, and cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32   nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state‐of‐the‐art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C _out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.