(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top-down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal-insulator-semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al₂O₃/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors.

An active-passivation p-GaN gate HEMT (AP-HEMT), featuring an active p-GaN passivation layer extending into the drain-side access region, is demonstrated on a commercial E-mode p-GaN/AlGaN/GaN heterostructure wafer. The active passivation layer (APL) is electrically connected to the p-GaN gate, and thus can supply/release mobile holes through gate electrode. The mobile holes in the APL effectively shields the overlaying surface traps from depleting the underlying 2DEG channel, and thus results in a much improved dynamic R _on . After a 10-ms 650-V V _DS stress, the measured dynamic R _on /static R _on is 4.30 for Conv-HEMT, but only 1.39 for AP-HEMT. Specially designed HEMTs with a surface testing electrode (ST) in the access region are fabricated to verify the screening effect. A negative V _ST mimics the virtual gate effect caused by negative surface charges, resulting in a reduced drain current in conventional HEMT (Conv-HEMT). In the AP-HEMT, a negative V _ST is shown to induce no change in the drain current, indicating an effective screening of the trap states. On the other hand, under a positive V _ST stress applied to a Conv-HEMT, electrons in the 2DEG channel are pulled over the AlGaN barrier and get trapped at the surface, resulting in a sharply decreased drain current after positive V _ST is removed. For the AP-HEMT, the drain current remain unchanged after the positive V _ST is removed. The actively passivated HEMT exhibits the highly desired suppression of surface trap induced dynamic R _on degradation.

In this letter, we report a quasi-vertical GaN Schottky barrier diode (SBD) fabricated on a hetero-epitaxial layer on silicon with low dislocation density and high carrier mobility. The reduction of dislocation is realized by inserting a thin layer with high density of Ga vacancies to promote the dislocation bending. The dislocation density is 1.6 × 10 ⁸ cm ^-2 with a GaN drift layer thickness of 4.5 μm. The fabricated prototype GaN SBD delivers a high on/off current ratio of 10 ¹⁰ , a high forward current density of 1.6 kA/cm ² @ ³ V, a low specific on-resistanceof 1.1 mQ·cm ² , and a low ideality factor of 1.23.

In this paper, we report the device performance of a high-voltage enhancement-mode (E-mode) GaN MOSHEMT on silicon substrate. Normally off operation is realized by a self-terminated precision gate recess process on an optimized high-electron mobility transistor structure. The GaN MOSHEMT is fully pinched off at zero gate bias, suggesting a “true” normally off operation. The threshold voltage is 0.4 V with a drain current density of 1 μA/mm as the criteria. The device with 15-μm gate-drain distance and 100-μm gate width exhibits a maximum drain current of 356 mA/mm at 8-V gate bias. The on/off current ratio of the device is larger than 1010 with a subthreshold slope of 80 mV/dec. The gate leakage current is below 10 ^-7 mA/mm up to 9-V gate bias. The off-state breakdown voltage (BV) is as high as 1528 V (880 V) measured with floating (grounded) silicon substrate at a drain leakage current criterion of 5 μA/mm. The specific on-resistance (RON,SP) of the device is 2.79 mΩ·cm ² , and the power figure of merit (BV ² /R _ON,SP ) is 277 MW/cm ² . High-voltage pulsed I-V measurement indicates that the dynamic on-resistance is only 1.6 times the static one with a pulsewidth of 10 μs at 400-V off-state quiescent drain bias. The high performance of the normally off GaN MOSHEMT is supposed to benefit from the high quality low pressure chemical vapor deposition Si ₃ N ₄ passivation layer and the advanced E-mode device fabrication process.

In this letter, we demonstrate a recessed-anode Schottky barrier diode (SBD) on a double AlGaN/GaN heterojunction structure. A self-terminated, oxidation/wet etching with low-pressure chemical vapor deposition (LPCVD) Si ₃ N ₄ mask is applied in the anode recess process. Unlike common plasma-based, dry etching techniques, the etched surface is not subjected to ion bombardment, and the etch depth is precisely controlled. As a result, a high effective channel mobility of 1079 cm ² /V · s is maintained in the channel beneath the recess surface. The fabricated devices with a 15-μm anode-to-cathode distance (L _AC ) are found to exhibit a uniform, low turn-ON voltage (V _ON ) of 0.69 ± 0.03 V, and a low specific on-resistance (R _ON,SP ) of 2.83 mQ · cm ² . The SBDs also show excellent off-state blocking characteristics due to the smooth recess interface together with the assistance of LPCVD grown Si ₃ N ₄ . A breakdown voltage of 1190 V is achieved for the SBDs with 15-μm L _AC at a leakage current criteria of 1 μA/mm, and the Baliga's figure-of-merit is 500 MW/cm ² .

To assess GaN power transistors’ capability to maintain a decent E-mode operation, ${V}_{\text {th}}$ at high ${V}_{\text {DS}}$ is measured for Schottky-type p-GaN gate HEMT, and an excessive negative ${V}_{\text {th}}$ shift is observed. With ${V}_{\text {DS}} =1$ V, ${V}_{\text {th}}$ is around 1.3 V at ${I}_{\text {D}} =1$ mA, but ${V}_{\text {th}}$ drops by ~0.6 V when measured at a high ${V}_{\text {DS}}$ of 100 V. In comparison, ohmic-type p-GaN gate HEMT only shows a negligible ${V}_{\text {th}}$ shift up to ${V}_{\text {DS}} =100$ V. A gate/drain coupled barrier lowering (GDCBL) effect is proposed to explain the appreciable ${V}_{\text {th}}$ shift in Schottky-type p-GaN gate HEMT. Upon high ${V}_{\text {DS}}$ , the potential of the floating p-GaN layer is raised by the drain through the capacitive coupling between p-GaN and drain ( ${C}_{\text {DP}}$ ). The positive potential of the p-GaN layer then lowers the energy barrier along the gated channel, resulting in a reduced ${V}_{\text {th}}$ . This effect is confirmed by the dependence of measured negative ${V}_{\text {th}}$ shift upon the property of gate/p-GaN contact and also by the numerical simulations that reveal the change in band diagrams upon high ${V}_{\text {DS}}$ .