Artificial neurons and synapses are critical units for processing intricate information in neuromorphic systems. Memristors are frequently engineered as artificial synapses due to their simple structures, gradually changing conductance and high-density integration. However, few studies have designed memristors as artificial neurons. In this letter, we demonstrate an integration-and-fire artificial neuron based on a Ag/SiO2/Au threshold switching memristor. This neuron displays four critical features for action-potential-based computing: the all-or-nothing spiking of an action potential, threshold-driven spiking, a refractory period, and a strength-modulated frequency response. As a post-synaptic neuron, the designed neuron was demonstrated to be applicable to digit recognition. These results demonstrate that the developed artificial neuron can realize the basic functions of spiking neurons and has great potential for neuromorphic computing.

Non-volatile computing-in-memory macros that are based on two-dimensional arrays of memristors are of use in the development of artificial intelligence edge devices. Scaling such systems to three-dimensional arrays could provide higher parallelism, capacity and density for the necessary vector–matrix multiplication operations. However, scaling to three dimensions is challenging due to manufacturing and device variability issues. Here we report a two-kilobit non-volatile computing-in-memory macro that is based on a three-dimensional vertical resistive random-access memory fabricated using a 55 nm complementary metal–oxide–semiconductor process. Our macro can perform 3D vector–matrix multiplication operations with an energy efficiency of 8.32 tera-operations per second per watt when the input, weight and output data are 8, 9 and 22 bits, respectively, and the bit density is 58.2 bit µm^–2. We show that the macro offers more accurate brain MRI edge detection and improved inference accuracy on the CIFAR-10 dataset than conventional methods.

Non-volatile computing-in-memory (nvCIM) can potentially meet the ever-increasing demands on improving the energy efficiency (EF) for intelligent edge devices. However, it still suffers from limited input parallelism due to the parasitic effects, signal margin degradation due to device non-idealities, and large hardware cost for analog readout. In this work, we present a two-transistor-one-resistor (2T1R) resistive memory (RRAM) nvCIM macro featuring: 1) a macro structure with decoupled memory and computing data paths; 2) the weighted hybrid 2T1R (WH-2T1R) cell array; 3) the redundant sub-array mapping scheme of the most-significant-bit (RSM-MSB); and 4) reference-subtracting current sense amplifier (RS-CSA). A test-chip is silicon-verified using the 28-nm high-k/metal-gate (HKMG) logic process with foundry-developed RRAM. The test-chip performs linear analog multiply-and-accumulate (MAC) operations over 32 accumulation channels and achieves 30.34–154.04 TOPS/W with 1-bit input (IN), 3-bit weight (W), and 4-bit output (O). Evaluations with the ResNet-18 model show that the MSB-RSM scheme results in 0.96% and 2.83% improvement on CIFAR-10 and CIFAR-100 inference accuracy, respectively.

Electrocardiogram (ECG) heartbeat classification plays a vital role in early diagnosis and effective treatment, which provide opportunities for earlier prevention and intervention. In an effort to continuously monitor and detect abnormalities in patients’ ECG signals on portable devices, this paper present a lightweight ECG heartbeat classification method based on a spiking neural network (SNN), a relatively shallow SNN model integrated with a channel-wise attentional module. We further explore the best-optimized architecture, which benefits from leveraging the full advantages of the SNN potential with the attention mechanism to process the classification task at low power and capture prominent features concerning the time, morphology, and multi-channel representations of the ECG signal. Results show that our model achieves overall classification accuracy of 98.26%, sensitivity of 94.75%, and F1 score of 89.09% on the MIT-BIH database, with energy consumption of 346.33 μJ per beat and runtime of 1.37 ms. Moreover, we have conducted multiple experiments to compare against current state-of-the-art methods using their assessment strategies to evaluate our model implementation on FPGA. So far, our work achieves comparable overall performance with all the literature in terms of classification accuracy, energy consumption, and real-time capability.

In this brief, an ultracompact and highly reliable physical unclonable function (PUF) is presented based on the mainstream resistive random access memory (RRAM) devices. With the entropy originating from the switching voltage between the high-resistance state (HRS) and the low-resistance state (LRS), the proposed RRAM PUF can be generated during the RRAM's standard SET operation, leading to minimized design overhead. In addition, different from the previous implementations where the adopted RRAM PUF cells are dedicated to the ``PUF'' function, the proposed RRAM PUF is fully reconfigurable between the ``PUF'' function and the normal memory function. Moreover, the proposed implementation is validated using a standard 0.13-μm CMOS process plus customized postprocessing dedicated to RRAM devices. Featuring a normalized PUF cell area of 108F², the native instability (i.e., unstable bits) is measured to be as low as 0.28% at the normal condition. With the operating temperature varying from -50 °C to 150 °C and the supply voltage varying from 4 to 6 V, the averaged bit error rate (BER) is reported to be as low as 0.06% and 0.095%, respectively.

In this paper, we present a fully reconfigurable resistive random access memory (RRAM) physical unclonable function (PUF) based on the truly random dynamic entropy of the ubiquitous jitter noise, which is intrinsically different from most previously demonstrated PUF implementations with semiconductor fabrication's process variation as the static entropy source. In addition, the proposed RRAM PUF is operated by configuring the mainstream RRAM cells to either high resistance state (for `1') or low resistance state (for `0'), according to the customized ring oscillator (RO) true random number generator's digital output that is determined by the random jitter noise. By completely removing the need of dedicated split resistance circuitry (SRC) in existing RRAM PUFs, the proposed implementation is fully compatible with the SET/RESET operations of the RRAM array for mainstream memory applications, leading to minimized design overhead and enhanced reliability without SRC-caused error bits. Fabricated using 130 nm standard complementary-metal-oxide-semiconductor (CMOS) process plus post-processing dedicated to the RRAM devices, the proposed RRAM PUF cell features an ultra-compact footprint of 1.82 μm² (i.e., 108 F²), which is capable of generating ~10⁷ PUF bits per cell due to the time-variant property of jitter noise and the full reconfigurability of the RRAM PUF. This significantly innovates all the previous weak PUF implementations based on the static entropy source of process variation, where the maximum bit number per PUF cell is always limited and fixed after the chip fabrication. Meanwhile, ultra-low native unstable bits of 0.28% and bit error rate (BER) per 10°C of 0.03% can be achieved for the fabricated RRAM PUF. Moreover, by passing the widely-adopted bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test under various VT conditions, the true randomness of the customized RO TRNG' dynamic entropy is validated using 65 nm standard CMOS process. Compared with the state-of-the-art weak PUF implementations, the native unstable bits is improved by 5.36x and the BER per 10°C is improved by 4x, even under the widest operating temperature range from -50°C to 150°C.