Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFETbased system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R _{on_sp} ) ratio (BV ² /R _{on_sp} ). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV ² /R _{on_sp} for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

This letter demonstrates an integration process of in situ Cl ^- doped Al ₂ O ₃ and gate recess technique to fabricate the enhancement mode AlGaN/GaN MOSHEMTs. The Cl ^- doped Al ₂ O ₃ thin film is deposited by the ultrasonic spray pyrolysis deposition and characterized by transmission electron microscopy and X-ray photoelectron spectroscopy. The relative permittivity of Cl ^- doped Al ₂ O ₃ is higher than the pure Al ₂ O ₃ and the output current is enhanced. The threshold voltage of the enhancement mode AlGaN/GaN MOSHEMT with the Cl ^- doped Al ₂ O ₃ gate dielectric layer rose from 0.2 to 1.3 V. Furthermore, the breakdown voltage of present enhancement mode AlGaN/GaN MOSHEMT reached 650 V. It was also found that the MOSHEMT with Cl ^- doped Al ₂ O ₃ has higher gate leakage than that with pure Al ₂ O ₃ . The thermal stability of threshold voltage and current collapse phenomenon is described in this letter.

Gate-all-around (GAA) MOSFETs relevant for the 11.9-nm CMOS technology node are optimized with device dimensions following the scale length rule. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for these well-tempered GAA structures. The tradeoff between read stability and write-ability of 6-T static RAM cell designs implemented with GAA MOSFETs with either square or rectangular nanowire channel regions is then investigated, and a calibrated transistor I-V compact model is used to estimate cell yield. The results indicate that a rectangular (thin and wide) channel design achieves the optimal balance between the read yield and write yield and hence provides for the lowest minimum cell operating voltage, estimated to be ~0.45 V, as well as smaller cell area.