The inclusion of machine-type communication in the 5G technology has motivated the research community to explore new derivative waveforms of orthogonal frequency division multiplexing. Filter bank multicarrier, universal filtered multicarrier (UFMC), and generalized frequency division multiplexing techniques are under evaluation with respect to their suitability to 5G requirements. In addition to acceptable spectral performance, investigation on computational complexity reduction while addressing flexibility can help in the selection of suitable waveform among multiple options available for 5G. In this regard, based on analysis of computation involved in UFMC waveform construction, few reduced complexity solution for UFMC transmitter implementations are recently proposed. However, hardware-implementation-related issues have not been discussed in detail. In this paper, we have proposed reduced complexity hardware solutions for all three constituent blocks, i.e., inverse discrete Fourier transform (IDFT), finite impulse response (FIR) filter, and spectrum shifting blocks of a UFMC transmitter. For IDFT part, a reduced complexity IFFT solution using Radix-2 decimation in a time technique is presented, where more than 42% computations can be avoided. It is also shown that how five times less number of multipliers can be used in an FIR filter to simplify filter architecture. Finally, a highly efficient method is presented to compute spectrum shifting coefficients through small sized lookup table.

The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over $GF\left(2^{233}\right)$. There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-$bit$ finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over $GF\left(2^{233}\right)$ on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.

Parallel-connected uninterruptible power supply (UPS) systems have been used to maintain power supply to the critical load in order to increase power capacity and system reliability. This paper presents a robust and precise voltage control strategy for parallel-connected UPS systems. Each parallel-connected UPS system consists of a three-phase inverter with an output inductor-capacitor (LC) filter directly connected to an AC common bus in order to feed the critical load. Fractional-order sliding mode control (FOSMC) is proposed to maintain the quality of the output voltage despite linear, unbalanced and/or nonlinear load condition. The Riemann-Liouville (RL) fractional derivative is employed in designing the sliding surface. The voltage control strategy effectively eliminates the parametric uncertainties, external disturbances, and reduce the total harmonic distortion (THD) of the output voltage. Furthermore, it also maintains very good voltage regulation such as dynamic response and steady-state error under the nonlinear or unbalanced load conditions. The stability of the proposed controller is proven by applying Lyapunov stability theory. Droop control approach and virtual output impedance (VOI) loop are investigated to guarantee the accurate active and reactive power-sharing for parallel-connected UPS system. Finally, the implementation of the control scheme is carried out by using MATLAB/Simulink real-time environment.

Universal filtered multicarrier (UFMC) is a low complexity promising waveform that provides quasi‐orthogonal property among subcarriers. In addition, it can achieve much better out‐of‐band emission performance than orthogonal frequency division multiplexing (OFDM) system. Authors have proposed a hardware platform to implement a UFMC transmitter in this paper. Highly reduced complexity schemes for IFFT, filtering, and spectrum shifting are realized on actual hardware. This helps to achieve overall architecture of the transmitter at the cost of minimal FPGA resource usage. Hence, the overall design uses only 1038 slice registers, 1154 slice LUTs, and 64 multipliers of Xilinx Virtex‐7 XC7VX330t device. A throughput of 773.5 Msamples/sec at an operational frequency of 364 MHz is achieved. This throughput is adequate for processing 50 Physical Resource Blocks (PRB) of LTE 10 MHz channelization in required time. The presented architecture provides a latency of only 2% of one LTE 10MHz channelization symbol due to the implementation of pipelining at different levels. Although the presented hardware design in its current form meets LTE 10MHz channelization throughput requirements, further increase in throughput is possible due to the scalable nature of the architecture. To the best of our knowledge, this work is first ever FPGA solution for UFMC transmitter presented in the literature.

An efficient hardware implementation of correlated Rayleigh fading channel simulator is presented in this paper. It emulates Doppler effects based on the use of Overlap-Save (OLS) method. OLS is used for both, the fading variates generator and the time domain interpolator, leading to a scalable complete solution. Moreover, additional simplifications were introduced to reduce even further algorithmic complexity when compared with the original OLS-based proposal. An efficient hardware implementation is achieved through maximizing the utilization rate of allocated hardware resources. When added to its scalability, this makes the proposal appealing to emulate channels with multipath effects for MIMO systems. Indeed, the proposed parallel architecture enables a throughput of 34 Mega Samples per Second per path at a clock frequency of 275 MHz on Xilinx Virtex-7 FPGA. The achieved throughput allows the support of the most demanding LTE configuration with 20 MHz channel bandwidth. To the best of our knowledge, this is the first ever real-time hardware implementation of OLS-based channel emulator.