The extraction of nitride trap density ( $N_{t}$ ) filled with electrons emitted by thermal emission (TE) in the charge-trapping layer of 3-D NAND flash memory is demonstrated. The intercell program (IP) pattern was adopted to intentionally inject electrons into the intercell region to minimize the influence of lateral migration (LM) on the trap profiles. This was confirmed by the retention characteristics observed at 120 °C, where the charge loss is mainly caused by the TE of the trapped electrons in the nitride layer. The extracted peak value of $N_{t}$ at $E_{C}$ - $E_{T}$ value of 1.20 eV using the IP pattern was as low as $1.01\times 10^{19}$ cm ⁻³ eV ⁻¹ , in the scan range of 0.96 eV to 1.27 eV. This value was 17% lower than that from the conventional adjacent cell program (P-P-P) pattern. Therefore, the IP pattern can be used in extracting trap profiles in the SiN layer in scaled 3-D NAND memories.

Decompositions of charge loss mechanisms in 3-D NAND flash memory with two different cell structures have been performed using high-temperature retention characteristics. It calculates emission rates of trap-to-band tunneling (TB) and band-to-trap tunneling (BT) to determine the dominant tunneling mechanisms. The lateral migration (LM) component is separated into the LM of holes (LMH) and electrons (LME) using the technology-computer-aided design (TCAD) simulation. The thicker blocking layer could lead to decreased vertical charge loss, and the shorter spacer could enhance the LM components.

Electrical characteristics with various program temperatures (T_PGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the T_PGM up to 120 °C and the read temperature (T_READ) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (I_BL) and threshold voltage (V_T). The V_T shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔV_T,CL) component and the poly-Si GB (ΔV_T,GB) component. The extracted ΔV_T,GB increases at higher T_PGM due to the reduced GB potential barrier. Additionally, the ΔV_T,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (X_GB) and the bit line voltage (V_BL).

The quantitative characteristics of traps created in the bandgap-engineered tunneling oxide (BE-TOX) layer and block layer after program/erase (P/E) stress-cycling in a 3D NAND flash memory were investigated. The trap spectroscopy by charge injection and sensing technique was used to obtain the distribution of traps in these layers. In the BE-TOX layer, significant traps were generated around 1.3 eV in the nitrogen-doped layer (N1) and increased by 48% in the fresh cell after P/E stress-cycling. The H bonds in the N1 are more likely to break during the stress-cycling and create neutral $\equiv \mathrm {SiO}^{\bullet }$ traps. In the block layer, however, trap generation was negligible after stress-cycling.

A novel dummy cell program (DMP) scheme has been introduced to enhance the retention characteristics of 3-D nand memory. This scheme programs dummy cells prior to the programming of target cells, aiming to induce a floating channel and reduce the channel potential. By programming dummy cells before target cells, the electric field in the tunneling oxide and charge trap layer (CTL) is alleviated, effectively mitigating both vertical and lateral charge loss mechanisms. Experimental characterization of threshold voltage ( ${V} _{T}\text {)}$ variations has been conducted based on program-verify (PV) levels and cell patterns. In the case of the erase-program–erase (EPE) pattern with PV7 dummy and PV3 target cells, a significant reduction of 31% in measured $\Delta {V} _{T}$ has been achieved. Notably, similar improvements are observed in the program-program–program (PPP) pattern. These findings strongly support the potential of the proposed DMP scheme in enhancing the reliability of flash memory.

The effects of single-event upset (SEU) on the threshold voltage ( ${V}_{T}$ ) of a programmed cell in 3-D charge-trap (CT) NAND flash memory have been investigated using 3-D technology-computer-aided design (TCAD) simulations. After ion strikes, the surrounding electric field ( ${E}$ -field) accelerates the generated holes into the CT layer (CTL), which lowers ${V}_{T}$ of the programmed cell. The tunneling oxide (TOX) strike causes a more severe ${V}_{T}$ shift than the blocking oxide (BOX) strike due to the higher ${E}$ -field in the TOX layer. As the strike angle increases from 0° (lateral) to 90° (vertical), the effective irradiation volume is reduced, resulting in the mitigation of the SEU influence. Scaling of cell dimensions becomes more vulnerable to SEU except for the thinner TOX.