This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.

This paper presents a novel `Cloud-based' solution for teaching computer networks in an educational context. One key advantage of the system is its ability to commission and decommission virtual infrastructures comprised of routers, switches and virtual machines on demand. It makes use of hardware located in different physical locations, VMWare software to manage the virtual resources and NetLab+ to manage the configuration of multiple different virtual scenarios. The key features of the cloud infrastructure are described and evaluated.

This paper deals with the analysis of an electronic load controller - also known as dump load - in order to improve the regulating behaviour in stand-alone generating systems. The considered dump load can be implemented in two alternatives. Each solution is analysed from the current harmonics injection point of view, through simulations and experimental trials

This paper is concerned with reliability analysis in relation to optimal switching of resonant power converters, aimed at minimizing their power loss and operational temperature and thus reducing their lifetime degradation. In most cases, high performance resonant converter control requires a continuous adaptation of the power device switching instances depending on the power input source, load current, or parameter variation in passive components. If the resonant converter is switched before or after the resonant swing ends, more loss is added to the system, with effects in operating temperature rise and reliability deterioration. Even if the switching frequency is adjusted to keep the output voltage constant, it may influence the operational temperature. This article is quantifying this problem with a calculation of the lifetime implication for both cases of Zero Voltage Transition (ZVT) and Zero Current Transition (ZCT) buck converters. A broad range of parameter variation in passive components is considered due to ageing or aggravated stress. A thorough performance (lifetime / reliability) evaluation is achieved through a comparative analysis of results obtained for resonant converters with ideal operation, resonant converters with adjusted timing due to parameter variation, and hard-switched converters without any resonance. Conclusions are formulated in the end. The results reported in the paper should be of high interests to the power electronics community, given that resonant converters are used in a wide range of applications due to their ability to reduce power semiconductor losses.

In this work, a novel lightweight and low energy encryption algorithm for voice over wireless networks is being developed and tested. The new encryption algorithm has to meet the QoS requirements of voice traffic and to be suitable for wireless devices. The goal of the research was to reduce the execution time and power consumption of the encryption process compared with the standard algorithm and at the same time at least to maintain or to increase its security level. The proposed algorithm employs similar methods with those used in the Advanced Encryption Standard algorithm (AES), with some changes and enhancements considering the limitations of wireless devices. The test results show significant improvements in new design metrics. A range of simulation scenarios are setup; testing data is analyzed to test delay, energy and security. Also, the comparison between the new algorithm and the standard one shows a significant amount of time and energy consumption reduction being achieved (approximately 35%), with good-level of complexity, making it more suitable for the wireless environment.