Copper sinter paste has been recently established as a robust die-attach material for high -power electronic packaging. This paper proposes and studies the implementation of copper sinter paste materials to create top-side interconnects, which can substitute wire bonds in power packages. Here, copper sinter paste was exploited as a fully printed interconnect and, additionally, as a copper clip-attach. The electrical and thermal performances of the copper-sinter paste interconnections (“sinterconnects”) were compared to a system with wire bonds. The results indicate comparable characteristics of the sinterconnect structures to the wire-bonded ones. Moreover, the performance of copper sinterconnects in a power module was further quantified at higher load currents via finite element analysis. It was identified that the full-area thermal and electrical contact facilitated by the planar sinterconnects can reduce ohmic losses and enhance the thermal management of the power packages.

Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors.

The hybrid integration of electronics in flexible substrates using fanned-out, wafer-level packaging (FOWLP) has recently gained significant attention, with numerous applications in wearable electronics, foldable displays, robotics, medical implants, and healthcare monitoring. In this study, a fully additive and scalable manufacturing process flow to realize a low-cost, flexible FOWLP system was introduced. Here, the integration of 36 LED chips in a biocompatible polydimethylsiloxane (PDMS) substrate was demonstrated using a stencil-printed silver (Ag) redistribution layer (RDL). The processes for the integration of chips, i.e., chip first (exposed die embedding), chip first (deep embedding with filled valleys) and chip last (RDL first), were implemented, and the corresponding samples were evaluated electrically. The bendability of the samples was also characterized at different bending diameters. Conclusively, it was shown that by using surface-modified PDMS as a flexible substrate and stretchable Ag paste as interconnect, flexible FOWLP can be produced.

The use of low-cost materials such as PET, paper, and unpackaged bare dies has become critical for cost-effective mass production, as demand for flexible hybrid electronics has skyrocketed, particularly for internet of things (IoT), electronic skin, and wearable applications. The advantages of this design include the sustainable use of resources, such as low-cost, readily accessible, and biologically degradable raw materials, and their suitability for printed electronics applications has been well researched. Mostly printed silver and sputtered silver has covered this market but has its own shortcomings. Combining this with techniques such as flip chip bonding and subtractive laser ablation provides us with the opportunity of fast fabrication and smaller size which can cater for new applications. In this study, we look at the flip chip bonding bare die to ablated copper on a PET substrate aided with anisotropic conductive paste. Furthermore, we investigate its reliability by performing bending tests.