Ariana Musello

Ms. Ariana Musello

Instituto de Micro y Nanoelectrónica (IMNE), USFQ
orcid

Research Focus & Metrics

Academic Career Length

6Years (2021-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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31 January 2023 in IEEE Transactions on Circuits and Systems II: Express Briefs
Verified
Journal Article
Open access
Ariana MuselloAriana Musello
Ariana Musello
Esteban GarzónEsteban Garzón
Esteban Garzón
MLMarco Lanuzza
Marco Lanuzza
LPLuis-Miguel Procel
Luis-Miguel Procel
RTRamiro Taco
Ramiro Taco
This brief presents an energy-efficient and highperformance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spintransfer torque magnetic RAM (STT-MRAM) based on doublebarrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

29 April 2021 in Electronics
Verified
Journal Article
Open access
PDF file
Kevin VicuñaKevin Vicuña
Kevin Vicuña
CMCristhopher Mosquera
Cristhopher Mosquera
Ariana MuselloAriana Musello
Ariana Musello
Sara BenedictisSara Benedictis
Sara Benedictis
MRMateo Rendón
Mateo Rendón
RTRamiro Taco
Ramiro Taco
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.