The defect-centric distribution is used, for the first time, to study the channel hot carrier (CHC) degradation. This distribution has been recently proposed for bias temperature instability (BTI) shift and we show that it also successfully describes the CHC behavior. This distribution has the advantage of being described by two physics-based parameters, the average threshold voltage shift produced by a single charge η and the number of stress-induced charged traps N _t . We study the behavior of η and N _t on nFETs with different geometries for different CHC stress times. As in the case of BTI, we observe that: 1) during the CHC stress, η is constant and N _t increases at the same rate of ΔV _th and 2) η scales as 1/Area. We show that the density of charged traps induced by CHC stress strongly increases with reducing channel length, in contrast to BTI, where the density of charged traps is independent of the device geometry. The defect analysis enabled by the defect-centric statistics can be used to deepen our understanding of CHC degradation in nanoscale MOSFETs, where the defects are reduced to a numerable level.

This brief presents an energy-efficient and highperformance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spintransfer torque magnetic RAM (STT-MRAM) based on doublebarrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

Miniaturization and portable devices have reshaped the electronic device landscape, emphasizing the importance of high performance while maintaining energy efficiency to ensure long battery life. FinFET and Tunnel-FET technologies have emerged as attractive alternatives to overcome the limitations of supply voltage scaling for ultra-low power applications. This work compares the performance of 10 nm FinFET- and TFET-based digital circuits from basic logic gates up to an 8k gates low-power microprocessor. When compared with their FinFET-based counterparts, the TFET-based logic gates have lower leakage power when operated below 300 mV, show higher input capacitance, and exhibit a reduced propagation delay under different fan-in and fan-out conditions. Our comparative study was extended to the synthesis of an MSP-430 microprocessor through standard cell libraries built particularly for this work. It is demonstrated that the TFET-based synthesized circuits operating at ultra-low voltages achieve a higher performance in terms of speed at the cost of increased power consumption. When the speed requirements are relaxed, the TFET-based designs are the most energy-efficient alternative. It is concluded that the TFET is an optimal solution for ultra-low voltage design.

This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

This paper studies the implementation of an algorithm to enhance the color of an image by considering global and local effects. The implementation is done on Matlab((and also on a FPGA using VHDL. The algorithm is called ACE (automatic color equalization). The paper presents the optimization of the algorithm using a subset or window. The algorithm performs the color enhancement automatically by equalizing the colors and improving the image. The results show an image with more contrast, higher number of details and visually better. Indeed, ACE maximizes the information of the image. The optimization of the algorithm reduces the complexity of the original one. Additionally, the VHDL implementation is quite faster than Matlab's.