Jose L. Martin

Prof. Dr. Jose L. Martin

orcid

Research Focus & Metrics

Academic Career Length

30Years (1997-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 October 2007 in Renewable and Sustainable Energy Reviews
Verified
Journal Article
Closed access
IAIñigo Martinez de Alegría
Iñigo Martinez de Alegría
JAJon Andreu
Jon Andreu
JMJose L. Martin
Jose L. Martin
PIPedro Ibañez
Pedro Ibañez
JVJosé Luis Villate
José Luis Villate
HCHaritza Camblong
Haritza Camblong

18 May 2010 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
EREider Robles
Eider Robles
SCSalvador Ceballos
Salvador Ceballos
Josep PouJosep Pou
Josep Pou
JMJose L. Martin
Jose L. Martin
Jordi ZaragozaJordi Zaragoza
Jordi Zaragoza
PIPedro Ibañez
Pedro Ibañez
This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.

17 July 2009 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
SCSalvador Ceballos
Salvador Ceballos
Josep PouJosep Pou
Josep Pou
EREider Robles
Eider Robles
Jordi ZaragozaJordi Zaragoza
Jordi Zaragoza
JMJose L. Martin
Jose L. Martin
This paper presents a study of the fault tolerance capacity of a neutral-point-clamped converter. Different faults in power semiconductors are considered, and the available postfault states of the converter are shown. In regard of the operation limits, two possible solutions are presented. In these solutions, adding a reduced number of additional components, the behavior of the converter when a switch fails improves considerably. Furthermore, an analysis of the neutral-point voltage balancing conditions after a fault and reconfiguration of the system is also evaluated. Experimental results that prove the correct operation of the proposed topologies are shown.

1 June 2009 in Renewable and Sustainable Energy Reviews
Verified
Journal Article
Closed access
IAIñigo Martínez de Alegría
Iñigo Martínez de Alegría
JMJose L. Martin
Jose L. Martin
IKIñigo Kortabarria
Iñigo Kortabarria
JAJon Andreu
Jon Andreu
PEPedro Ibañez Ereño
Pedro Ibañez Ereño

23 August 2010 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
SCSalvador Ceballos
Salvador Ceballos
Josep PouJosep Pou
Josep Pou
Jordi ZaragozaJordi Zaragoza
Jordi Zaragoza
EREider Robles
Eider Robles
JVJosé Luis Villate
José Luis Villate
JMJose L. Martin
Jose L. Martin
This paper presents a new three-level topology based on the neutral-point (NP)-clamped converter. An additional leg is added to the basic topology. The main purpose of this leg is to provide the converter with fault-tolerant capabilities. In addition, during normal operation mode, the fourth leg can be used to balance the NP voltage. In this way, the low-frequency voltage oscillations that appear in the NP under some operating conditions are cancelled out effectively. As a result, the modulation strategy of the three main legs of the converter does not have to take care of the voltage balance and can focus on other aspects such as, for instance, minimizing the switching losses of the converter. However, the inclusion of the fourth leg produces some additional losses. A resonant topology is proposed to minimize the switching losses of this leg. Three different fault-tolerant solutions based on the fourth-leg topology are presented. A comparison of these topologies showing their respective advantages and drawbacks is made. Experimental results are presented to show the viability of this approach.

3 March 2008 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
SCSalvador Ceballos
Salvador Ceballos
Josep PouJosep Pou
Josep Pou
Jordi ZaragozaJordi Zaragoza
Jordi Zaragoza
JMJose L. Martin
Jose L. Martin
EREider Robles
Eider Robles
PIPedro Ibanez
Pedro Ibanez
This paper presents a new low-loss modulation technique for the hybrid three-level four-leg converter. The total losses of the converter are reduced by about 18% on average compared to the standard three-leg neutral-point-clamped converter. Furthermore, the low-frequency voltage oscillation in the neutral point is completely cancelled, and the maximum benefit of the dc-link voltage is obtained. All these facts, together with the fault-tolerant ability due to the fourth leg, make this topology very interesting for applications such as wind generation, in which it is important to maximize efficiency and reliability. Some experimental results confirm the good performance of the proposed modulation technique.