Performance of a carrier-based pulsewidth modulation (CB-PWM) strategy can be improved by the inclusion of a zero-sequence voltage in the modulation-reference signal. This paper proposes a new CB-PWM strategy for a three-level neutral-point-clamped (NPC) converter, which is based on a zero-sequence voltage injection. By inclusion of the zero-sequence voltage, the sinusoidal-modulation reference is modified to 1) carry out the voltage-balancing task of the dc-link capacitors, with no additional control effort, 2) reduce the switching losses, and 3) reduce the low-frequency voltage oscillations of the neutral point. The proposed strategy is an alternative approach to the nearest three-vector (NTV) space-vector modulation (SVM) strategy and is obtained by the analysis of the NTV-SVM strategy and establishing a correlation between the NTV-SVM and the CB-PWM strategies. The salient features of the proposed scheme, as compared with the NTV-SVM strategy, are: 1) its reduced computational processing time which is attractive for digital implementation and 2) its reduced switching losses. Compared with the existing CB-PWM strategies, the proposed strategy offers 1) capability to balance the capacitor voltages and reduce the NP voltage oscillations and 2) reduced switching losses. Performance of the proposed CB-PWM strategy for a three-level NPC converter based on time-domain simulation studies in the MATLAB/SIMULINK environment is evaluated and also experimentally verified.

This paper studies different circulating current references for the modular multilevel converter. The circulating current references are obtained from the instantaneous values of the output current and modulation signal of the phase leg. Therefore, the determination of the amplitude and phase of the output current is not needed, which is a significant improvement compared to other methods such as those based on injecting specific harmonics in the circulating currents. Among the different methods studied in this paper, a new method is introduced, which is able to reduce the capacitor voltage ripples compared to the other methods. A closed-loop control is also proposed which is able to track the circulating current references. With the discussed methods, the average values of the capacitor voltages are maintained at their reference while the voltage ripples are kept low. Experimental results are presented to demonstrate the effectiveness of the proposed and discussed methods.

This paper presents a novel modulation strategy for a neutral-point-clamped converter. This strategy overcomes one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point under some operating conditions. The proposed modulation strategy can completely remove this oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads. The algorithm is based on a carrier-based pulsewidth modulation. Nevertheless, it can generate the maximum output-voltage amplitudes that are attainable under linear modulation, such as space-vector modulation. Furthermore, this technique can be implemented with a very simple algorithm and, hence, can be processed very quickly. The only drawback of this strategy is that the switching frequencies of the devices are one third higher than those of standard sinusoidal pulsewidth modulation. A control loop for balancing the voltages on the dc-link capacitors is also proposed. This balancing strategy is designed, so that it does not further increase the switching frequencies of the devices when it is applied to the converter. The proposed modulation technique is verified by simulation and experiment.

This paper presents a hybrid modulation technique for the three-level neutral-point-clamped converter. A modulation strategy, based on two modulation signals per phase, was presented previously. This strategy completely removes the low-frequency voltage oscillations that appear at the neutral point (NP) in some operation conditions. However, it also has a major drawback: it significantly increases the switching losses of the converter. The proposal in this paper combines such a modulation strategy with sinusoidal pulsewidth modulation (SPWM). The main characteristic of this hybrid modulation is the reduction in switching losses at the cost of some low-frequency voltage oscillations at the NP. The amplitude of these oscillations can be controlled by varying the combination of the two strategies. The performance of the hybrid modulation is analyzed and compared with the original strategies. Power losses and oscillation amplitudes on the dc-link capacitors are evaluated. Experimental results show how the hybrid modulation performs by balancing the dc-link capacitors.

This paper proposes an algorithm to calculate the optimal amplitude and phase of the harmonic current components that can be injected in the circulating currents of a modular multilevel converter (MMC) to minimize the capacitor voltage fluctuations. An optimal second harmonic component and an optimal set of second and fourth harmonic components are proposed. Simulation results are obtained in MATLAB/Simulink environment to study the effectiveness of the calculated optimal currents. Selected experimental results have been obtained from an MMC laboratory prototype, testing the effects of the circulating currents. The reported results demonstrate the effectiveness of using a fourth harmonic component in the circulating current, which improves the effect of the second harmonic on reducing the capacitor voltage fluctuations.

This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.