A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based $4^{\mathbf {th}}$ -order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ( $\text{S}_{{21}}$ ) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of $>\!\!\!-12.8$ dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows $\text{S}_{{21}}$ of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm ² . The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively.

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13-μm CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-connected loads to reduce the noise contribution originated from CGCS transistors and enhance the linearity due to post linearization. The auxiliary common-source (CS) amplifier with a diode-connected is added to reduce the overall noise figure (NF) of the LNA by sharing an input signal with CGCS transistors and applying its output signal to the diode-connected load of CS transistor. Because the voltage gain of the LNA is determined by the transconductance (gₘ) ratio of the same types of nMOS transistors, its power gain (S₂₁) and NF are quite roust over PVT variations. In experiments, it showed S₂₁ of 14 dB and NF of 4 dB with an input return loss (S₁₁) of greater than 10 dB at 450 MHz. Concerning voltage variation (1.08-1.32 V) and temperature variation (-20 °C ~ +80 °C), the worst variations in S₂₁ and NF were approximately 1.4 and 1.1 dB, respectively.

A sub-GHz/2.4 GHz highly selective reconfigurable RF front-end employing $N$ -path complementary balun-LNA and linearized RF-to-BB current-reuse (CR) mixer is proposed to implement internet-of-things (IoT) devices supporting short-and long-range wireless connectivity technologies. The proposed balun-LNA is built based on an active feedback common-source (CS) amplifier with a common-gate common-source (CGCS) balun load. A complementary version is devised to avoid a severe voltage drop across the resistor load attaining sufficiently high gain and increased effective transconductance without additional current consumption. In addition, an 8-path notch filter is added at a feedback path to improve LNA selectivity in sub-GHz. At 2.4 GHz, an inductive source degenerated LNA (ISDLNA) is used to achieve low noise figure (NF). The proposed RF-to-BB current-reuse mixer employed a second-order-intermodulation (IM2) injection technique for the linearization of the RF front-end. The IM2 injection technique improves linearity by generating the in-phase fundamental signal and out-of-phase third-order-intermodulation (IM3) signal, compared to the passive mixer output. The auxiliary path for the linearization is designed to consume ultra-low power by employing a newly proposed current-reuse-based differential IM2 generator, passive multiplier, and current-steering-based summing stage. As a result, the proposed RF-to-BB CR mixer alleviates the loading effect for the balun-LNA while achieving better gain, NF, and linearity with low power consumption. In measurement, the proposed front-end achieved the conversion gain of 50.5 $\sim$ 44.4 dB and 39.4 dB and double-sideband noise figure (NF $_{\mathrm{DSB}})$ of 4.4 $\sim$ 5.7 dB and 5.3 dB, respectively, in sub-GHz and 2.4 GHz. It also achieved in-band and out-of-band input-referred third-order intercept point (IIP3) from $-$ 18.0 to $-$ 15.2 dBm and from $-$ 0.4 to $-$ 2.6 dBm in sub-GHz and, the in-band IIP3 of $-$ 15.0 dBm at 2.4 GHz. The chip area of the proposed RF front-end core was less than 1.3 mm $^{2}$ excluding the measurement buffer and I/O PADs.

A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves >40.3 dB conversion gain, -35.8 dBm in-band input-referred third-order intercept point (IIP3), >-22.3 dBm out-of-band IIP3, and an average 3^rd LO HRR of 43 dB over 300-800 MHz in DBM&HR mode. Over 600-1200 MHz in SHM mode, it shows >31.8 dB conversion gain, -30.9 dBm in-band IIP3, and >-20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage.

An analog baseband (ABB) spectrum sensing circuit is proposed for fast spectrum sensing. Contrast to the conventional RF scanner where it takes a relatively long period to detect channel and interference condition by sequentially controlling the center frequency of the filter, the proposed ABB circuit can scan it at a time using different bandwidths of lowpass filters with an almost equal out-of-band attenuation slope to sense the powers and frequencies of channel and interference. The ABB circuit is composed of two chains of five cascaded real and complex low-pass filters. The cut-off frequencies of five cascaded low-pass filters are set to be 10, 8, 6, 4 and 2 MHz respectively, regarding the channel bandwidth of 2 MHz. The orders of the five filters are optimized to be 4th, 4th, 3rd, 2nd, and 2nd order respectively to make the rejected out-of-band power same for each filter for accurate detection. The filter core is designed on the basis of a flipped voltage follower and a super source follower for a low power dissipation and a high linearity, and the low power technique for implementing high-order filter is newly proposed in the design of filter chain. The measured frequency response at each output of the filter chain was almost the same to the simulation result. The measurement results show a noise figure (NF) of 19.2 dB, 22.1 dB, 24.8 dB, 25.1 dB, and 27 dB for each filters, and an in-band input-referred third-order intercept point (IIP3) of 9.2 dBm, 7.2 dBm, and 15.7 dBm at the output of 1st, 3rd, and last stages. The total power consumption of the filter chain is 10.4 mW from a 1.2 V supply voltage.

A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (V_th) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load R_opt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × V_DD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show R_opt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (P_sat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a P_sat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a P_sat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.