A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based $4^{\mathbf {th}}$ -order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ( $\text{S}_{{21}}$ ) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of $>\!\!\!-12.8$ dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows $\text{S}_{{21}}$ of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm ² . The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively.

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13-μm CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-connected loads to reduce the noise contribution originated from CGCS transistors and enhance the linearity due to post linearization. The auxiliary common-source (CS) amplifier with a diode-connected is added to reduce the overall noise figure (NF) of the LNA by sharing an input signal with CGCS transistors and applying its output signal to the diode-connected load of CS transistor. Because the voltage gain of the LNA is determined by the transconductance (gₘ) ratio of the same types of nMOS transistors, its power gain (S₂₁) and NF are quite roust over PVT variations. In experiments, it showed S₂₁ of 14 dB and NF of 4 dB with an input return loss (S₁₁) of greater than 10 dB at 450 MHz. Concerning voltage variation (1.08-1.32 V) and temperature variation (-20 °C ~ +80 °C), the worst variations in S₂₁ and NF were approximately 1.4 and 1.1 dB, respectively.

A 2.4 GHz reconfigurable cascode/folded-cascode inductive source degenerated LNA (ISDLNA) is proposed to implement the variable-gain functionality with enhanced output 1 dB compression point (OP1dB) and output third-order intercept point (OIP3) over the gain reduction, ensuring low noise figure (NF) of sub-1 dB at high gain mode. Depending on the channel condition, the LNA is designed to be operated as the cascode and folded-cascode ISDLNA through the digital switch control to have low NF of around 1 dB at high gain mode and high input P1dB (IP1dB) of greater than −5 dBm at low gain mode, respectively. To avoid the reliability issues caused by the overdriving control voltage of greater than the nominal supply voltage, the transmission gate switch is employed as the common gate stage of the cascode amplifier. In experiments, the proposed variable-gain LNA shows a power gain $(S_{21})$ , input return loss $(S_{11})$ , and NF of 11.8 dB, −31.8 dB, and 1.1 dB at high gain mode, and 5.0 dB, −14.4 dB, and 1.96 dB at low gain mode. In case of the linearity, the proposed LNA shows an IP1dB and input IP3 (IIP3) of −19.2 dBm and −5 dBm at high gain mode, and −5.1 dBm and +4.8 dBm at low gain mode, respectively. The power consumption for two operation modes is the same as 9.6 mW from a 1.2 V supply voltage.

A CMOS up-conversion mixer with an intermediate frequency (IF) amplifier and local oscillator (LO) buffer is presented for mobile 28-GHz-band 5G dual-conversion transceivers. A balun transformer with improved common-mode rejection ratio characteristics is proposed to improve the LO second-harmonic signal suppression, which is a problem in the up-conversion mixer of the 5G dual-conversion architecture. By applying the proposed balun transformer instead of the conventional one, a common-mode rejection ratio greater than 10 dB can be achieved at the frequencies of the LO second-harmonic leakage signal. An up-conversion mixer with an IF amplifier and LO buffer incorporating the proposed balun transformer was implemented in a 65-nm CMOS process, and it draws a current of 31.4 mA from a 1-V supply voltage. It provides a gain larger than 22.2 dB, a noise figure less than 4.1 dB, a thirdorder output intercept point higher than 4.6 dBm, and an LO second-harmonic leakage signal lower than -55.5 dBm in frequencies ranging from 26.5 GHz to 29.5 GHz. It also exhibits a suppression improvement of the LO second-harmonic leakage signal of approximately 14 dB with respect to an up-conversion mixer with IF amplifier and LO buffer using the conventional balun transformer. The proposed up-mixer with IF amplifier and LO buffer is the first one reported that addresses the 2LO leakage issue and the first demonstration of 2LO leakage signal suppression improvement for a 5G mmWave dual-conversion single-quadrature transmitter.

A low‐phase noise ring voltage‐controlled oscillator (VCO) employing input‐coupled dynamic current source is presented. By simply coupling the input signal to the gate node of the current source transistor, the proposed inverter has a larger output swing and steeper maximum slope than conventional structures, which directly results in phase noise improvement. Under the same conditions, compared to the conventional structure, the proposed ring VCO achieves 7.5 and 11 dB of phase noise improvement at 100 kHz and 1 MHz offset frequencies, respectively. The proposed ring VCO has a tuning range of 823–1300 MHz and post‐layout simulation shows a figure‐of‐merit of 159–162 dBc/Hz in the entire oscillation frequency range. In the measurement results,the authors recorded a phase noise of −106 dBc/Hz and figure‐of‐merit reaching 165 dBc/Hz at 1 MHz offset frequency, consuming 1.2 mW from a 1.8 V supply at 1 GHz oscillation frequency. The proposed ring VCO is implemented in 180 nm CMOS process and occupies a size of 0.0024 mm ² .

A sub-GHz/2.4 GHz highly selective reconfigurable RF front-end employing $N$ -path complementary balun-LNA and linearized RF-to-BB current-reuse (CR) mixer is proposed to implement internet-of-things (IoT) devices supporting short-and long-range wireless connectivity technologies. The proposed balun-LNA is built based on an active feedback common-source (CS) amplifier with a common-gate common-source (CGCS) balun load. A complementary version is devised to avoid a severe voltage drop across the resistor load attaining sufficiently high gain and increased effective transconductance without additional current consumption. In addition, an 8-path notch filter is added at a feedback path to improve LNA selectivity in sub-GHz. At 2.4 GHz, an inductive source degenerated LNA (ISDLNA) is used to achieve low noise figure (NF). The proposed RF-to-BB current-reuse mixer employed a second-order-intermodulation (IM2) injection technique for the linearization of the RF front-end. The IM2 injection technique improves linearity by generating the in-phase fundamental signal and out-of-phase third-order-intermodulation (IM3) signal, compared to the passive mixer output. The auxiliary path for the linearization is designed to consume ultra-low power by employing a newly proposed current-reuse-based differential IM2 generator, passive multiplier, and current-steering-based summing stage. As a result, the proposed RF-to-BB CR mixer alleviates the loading effect for the balun-LNA while achieving better gain, NF, and linearity with low power consumption. In measurement, the proposed front-end achieved the conversion gain of 50.5 $\sim$ 44.4 dB and 39.4 dB and double-sideband noise figure (NF $_{\mathrm{DSB}})$ of 4.4 $\sim$ 5.7 dB and 5.3 dB, respectively, in sub-GHz and 2.4 GHz. It also achieved in-band and out-of-band input-referred third-order intercept point (IIP3) from $-$ 18.0 to $-$ 15.2 dBm and from $-$ 0.4 to $-$ 2.6 dBm in sub-GHz and, the in-band IIP3 of $-$ 15.0 dBm at 2.4 GHz. The chip area of the proposed RF front-end core was less than 1.3 mm $^{2}$ excluding the measurement buffer and I/O PADs.