A versatile resistive temperature sensor for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture. This allows efficient scaling of power with conversion rate, enables optional oversampling for an adaptable resolution, and provides efficient adaptability to different resistor values. A new double-sided measurement mode is proposed to compensate for offset, 1/f noise and non-idealities at system level. The sensor achieves a minimum power consumption of 174pW at 1S/s measurement rate, which scales up to 488.3nW at 100kS/s. It offers a nominal rms resolution of 0.61∘C and a resolution FoM as low as 1.82pJ∙∘C2.

This article presents a second-order noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital-predicted mismatch error shaping (MES). The loop filter is composed of an active amplifier and two cascaded passive integrators to provide a theoretical 30-dB in-band noise attenuation. The amplifier achieves $18\times $ gain in a power-efficient way thanks to its inverter-based topology and duty-cycled operation. The capacitor mismatch in the digital-to-analog converter (DAC) array is mitigated by first-order MES. A two-level digital prediction scheme is adopted with MES to avoid input range loss. Fabricated in 65-nm CMOS technology, the prototype achieves 80-dB peak signal-to-noise-and-distortion-ratio (SNDR) and 98-dB peak spurious-free-dynamic-range (SFDR) in a 31.25-kHz bandwidth with $16\times $ oversampling ratio (OSR), leading to a Schreier figure-of-merit (FoM) of 176.3 dB and a Walden FoM of 14.3 fJ/conversion-step.

Advancements in the field of flexible electronics have enabled many novel applications such as wearables, flexible large-area displays, and textile-based sensor systems. A widely used semiconductor material for flexible electronics is amorphous indium gallium zinc oxide (a-IGZO). When compared to other semiconductors suitable for flexible technologies, this material is attractive for its higher mobility, better bias stability and improved uniformity. This paper presents an overview of current trends in analog and mixed signal circuit design and in architectures for a-IGZO TFT based sensor systems. We highlight the specific design challenges associated with the main sub-blocks found in sensors and bio-signal acquisition systems based on a-IGZO TFT technologies: front-end amplifiers and data converters. We then present an overview of several state-of-the-art sensor systems based on a-IGZO TFTs and their applications. Finally, conclusions are drawn, and a roadmap for the future development of analog and mixed signal circuit design in a-IGZO TFT is presented.

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison techniques. A pre-comparison technique is proposed to solve the over-range problem caused by MES. With MES and pre-comparison, the digital-to-analog converter (DAC) mismatch error can be first-order shaped, while a full input range is maintained. Besides, data-driven noise reduction and chopping techniques are combined to reduce the comparator noise efficiently. The prototype in 65-nm CMOS achieves 84.5-dB signal-to-noise-and-distortion ratio (SNDR) and 103-dB spurious-free dynamic range (SFDR) in a 4-kHz bandwidth, with a power consumption of 0.98 $\mu \text{W}$ from a single 0.8-V supply and an area of 0.033 mm ² , resulting in a Schreier figure of merit (FoM) of 180.6 dB and a Walden FoM of 8.9 fJ/conversion-step, respectively. Among ADCs with above 100-dB SFDR, this is the smallest design without calibration and the only sub- $\mu \text{W}$ and sub-1-V design. These features make it suitable for high-resolution and low-cost applications.

This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm $^{2}$ . In a 20 kHz bandwidth, the LC-ADC achieves a 64 dB SNDR. Thanks to the proposed techniques a power efficiency of up to 1.8 fJ/conv.-step is achieved for sinusoidal inputs. For sparse biopotential signals, a FoM $_{\text{W}}$ as low as 0.9 fJ/conv.-step was measured. This makes the prototype interesting for e.g., biomedical applications that make use of spike-based processing.

This work describes a miniature, ultra-low power, all-dynamic temperature sensor based on a duty-cycled resistive transducer bridge and a 9 bit asynchronous SAR ADC in 65nm CMOS. It features a novel floating bridge technique and automatic power gating to achieve the lowest reported power consumption. It consumes 2.18pJ per conversion and has an RMS resolution of 0.53K, leading to a FoM of 0.61pJ∙K. A standby power of 52pW allows a high power-efficiency, even at low sample rates. It occupies 36x46μm of chip area and has a sensing range from -20 to 120∘C.