A versatile resistive temperature sensor for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture. This allows efficient scaling of power with conversion rate, enables optional oversampling for an adaptable resolution, and provides efficient adaptability to different resistor values. A new double-sided measurement mode is proposed to compensate for offset, 1/f noise and non-idealities at system level. The sensor achieves a minimum power consumption of 174pW at 1S/s measurement rate, which scales up to 488.3nW at 100kS/s. It offers a nominal rms resolution of 0.61∘C and a resolution FoM as low as 1.82pJ∙∘C2.

This article presents a second-order noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital-predicted mismatch error shaping (MES). The loop filter is composed of an active amplifier and two cascaded passive integrators to provide a theoretical 30-dB in-band noise attenuation. The amplifier achieves $18\times $ gain in a power-efficient way thanks to its inverter-based topology and duty-cycled operation. The capacitor mismatch in the digital-to-analog converter (DAC) array is mitigated by first-order MES. A two-level digital prediction scheme is adopted with MES to avoid input range loss. Fabricated in 65-nm CMOS technology, the prototype achieves 80-dB peak signal-to-noise-and-distortion-ratio (SNDR) and 98-dB peak spurious-free-dynamic-range (SFDR) in a 31.25-kHz bandwidth with $16\times $ oversampling ratio (OSR), leading to a Schreier figure-of-merit (FoM) of 176.3 dB and a Walden FoM of 14.3 fJ/conversion-step.

A versatile, low-power, and energy-efficient capacitance-to-digital converter (CDC) for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture with adaptable speed, resolution, and range. The proposed CDC includes a single-armed capacitive bridge and a differential switched-capacitor 10-b asynchronous successive approximation register (SAR) analog-to-digital-converter (ADC). The bridge output is directly sampled by the ADC through fully passive correlated-double-sampling (CDS) approach, which enables a fully dynamic operation. The design is fabricated in a 65-nm CMOS technology. Thanks to the dynamic nature of the CDC, sampling rates from 1 S/s up to 100 kS/s are supported and capacitances from 1.23 to 24.59 pF can be digitized, while the power scales inherently from 0.1 nW to 1 μW. Optionally, the range can be further extended to >100 pF, and oversampling can be used to enhance resolution. This makes the design versatile to efficiently deal with a variety of sensors having different speed and resolution requirements and different capacitance values. The 0.1 nW lowest absolute power is >20x smaller than the prior art, and the figure of merit (FoM) from 18 to 59 fJ/conv-step is also the lowest among prior designs. To provide application examples, this chip is further verified with a microelectromechanical (MEMS) pressure sensor and a MEMS accelerometer. It can measure environmental pressure consuming only 0.8 nW at a speed of 100 S/s, and measure acceleration using 1.4 nW at a speed of 200 S/s.

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison techniques. A pre-comparison technique is proposed to solve the over-range problem caused by MES. With MES and pre-comparison, the digital-to-analog converter (DAC) mismatch error can be first-order shaped, while a full input range is maintained. Besides, data-driven noise reduction and chopping techniques are combined to reduce the comparator noise efficiently. The prototype in 65-nm CMOS achieves 84.5-dB signal-to-noise-and-distortion ratio (SNDR) and 103-dB spurious-free dynamic range (SFDR) in a 4-kHz bandwidth, with a power consumption of 0.98 $\mu \text{W}$ from a single 0.8-V supply and an area of 0.033 mm ² , resulting in a Schreier figure of merit (FoM) of 180.6 dB and a Walden FoM of 8.9 fJ/conversion-step, respectively. Among ADCs with above 100-dB SFDR, this is the smallest design without calibration and the only sub- $\mu \text{W}$ and sub-1-V design. These features make it suitable for high-resolution and low-cost applications.

This work describes a miniature, ultra-low power, all-dynamic temperature sensor based on a duty-cycled resistive transducer bridge and a 9 bit asynchronous SAR ADC in 65nm CMOS. It features a novel floating bridge technique and automatic power gating to achieve the lowest reported power consumption. It consumes 2.18pJ per conversion and has an RMS resolution of 0.53K, leading to a FoM of 0.61pJ∙K. A standby power of 52pW allows a high power-efficiency, even at low sample rates. It occupies 36x46μm of chip area and has a sensing range from -20 to 120∘C.

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This paper reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing ΔΣ modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on ΔΣ modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end’s residue, resulting in high resolution and excellent energy efficiency simultaneously.