In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this paper proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that form a circularly linked schematic. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91% compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

The continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells.

With the rapid advancement of semiconductor technologies, latches become increasingly sensitive to soft errors, especially triple node upsets (TNUs), in harsh radiation environments. In this article, we first propose a high-performance and area-efficient latch, namely, HALTRAV, featuring complete TNU-recovery. The storage portion of HALTRAV consists of 28 interlocked source-drain cross-coupled inverters (SCIs) for complete TNU-recovery with area efficiency and low delay. To mitigate the issue that node-upset-recovery verifications for existing latches highly relies on electronic design automation tools, we further propose an algorithm-based verification method that can automatically verify the node-upset-recovery of latches, which greatly simplifies the reliability-verification flow. Simulation results demonstrate the TNU-recovery of HALTRAV and also show that HALTRAV achieves 40.38%, 8.17%, and 31.89% reduction in delay, area, and delay-power–area product (DPAP) on average, respectively; however; it is at the cost of power as compared to typical latches that are TNU-recoverable. Comparison results also demonstrate the moderate sensitivity of HALTRAV to the impacts of the process, voltage, and temperature (PVT) variations.

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead.

The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as double-node upsets (DNUs), are typical soft errors. This paper proposes two radiation-hardened FF designs, namely DNU-tolerant FF (DUT-FF) and DNU-recoverable FF (DUR-FF). First, the DUT-FF which mainly consists of four dual-interlocked-storage-cells (DICEs) and three 2-input C-elements, is proposed. Then, to provide complete self-recovery from DNUs, the DUR-FF which mainly uses six interlocked DICEs is proposed. They have the following advantages: (1) They can completely protect against SNUs as well as DNUs; (2) the DUT-FF is cost-effective but the DUR-FF can provide complete self-recovery from any DNU. Simulations show the complete SNU/DNU tolerance of DUT-FF and the complete SNU/DNU self-recovery of DUR-FF but at the cost of indispensable area overhead when compared to the SNU hardened FFs. Besides, compared to the FFs of the same-type, the proposed FFs achieve a low delay making them suitable for high-performance applications.