We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148 $\boldsymbol {\mu }\mathbf {V_{rms}}$ input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14 ${\mu }\text{V}$ . Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost ${\pm 2\pi }$ input phase range, the maximum operating frequency of the PFD is 1.32 GHz.

We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 $\mu \text{m}$ CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is −147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm2. A state-variable MATLAB® model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth.

This brief describes an improved CMOS thyristor-based delay element (THDE) in which two current sources, digitally-controlled (DC) and voltage-controlled (VC), are implemented to demonstrate the design choice trade-offs and offer a wide range of delays. Both THDE designs show reduced temperature sensitivity while allowing an extended tuning range. Prototypes fabricated in a 0.35-μm CMOS process exhibit measured delay range of 26 ns-4.5 μs for DC-based delay element and 16 μs-5 ms for VC-based delay element. At their maximum delay amounts, the integrated THDEs consume 4.1 and 1.58 μW, respectively, from a 3.3-V supply. Also, the fabricated delay cells show a temperature sensitivity of 900 and 2710 ppm/∘C, respectively, when operating at maximum delay.

We describe in the paper a ring voltage-controlled oscillator (VCO) indicating an improved phase noise over a wide range of frequency offsets and an extended frequency/voltage tuning range. The phase noise is improved by leveraging a better linearity approach, while reducing the VCO gain and maintaining wide tuning range. The proposed VCO is a block of a time-domain comparator embedded in a monitoring and readout circuit of an industrial sensor interface. An analytical model is extracted resulting in closed-form expressions for both input-referred noise and phase noise of the VCO. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The prototype of the proposed VCO was implemented and fabricated in a 0.35 µm CMOS process. The integrated VCO consumes 0.903 mW from a 3.3 V supply, when running at its maximum frequency of 9.37 MHz. The measured phase noise of the proposed VCO is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the occupied silicon area of circuit is 0.005 mm2.