Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm² panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

We report on the cure characterization, based on inline monitoring of the dielectric parameters, of a commercially available epoxy phenol resin molding compound with a high glass transition temperature (>195 °C), which is suitable for the direct packaging of electronic components. The resin was cured under isothermal temperatures close to general process conditions (165–185 °C). The material conversion was determined by measuring the ion viscosity. The change of the ion viscosity as a function of time and temperature was used to characterize the cross-linking behavior, following two separate approaches (model based and isoconversional). The determined kinetic parameters are in good agreement with those reported in the literature for EMCs and lead to accurate cure predictions under process-near conditions. Furthermore, the kinetic models based on dielectric analysis (DEA) were compared with standard offline differential scanning calorimetry (DSC) models, which were based on dynamic measurements. Many of the determined kinetic parameters had similar values for the different approaches. Major deviations were found for the parameters linked to the end of the reaction where vitrification phenomena occur under process-related conditions. The glass transition temperature of the inline molded parts was determined via thermomechanical analysis (TMA) to confirm the vitrification effect. The similarities and differences between the resulting kinetics models of the two different measurement techniques are presented and it is shown how dielectric analysis can be of high relevance for the characterization of the curing reaction under conditions close to series production.

Liquid crystal polymer (LCP) has gained wide interest in the electronics industry largely due to its flexibility, stable insulation and dielectric properties and chip integration capabilities. Recently, LCP has also been investigated as a biocompatible substrate for the fabrication of multielectrode arrays. Realizing a fully implantable LCP-based bioelectronic device, however, still necessitates a low form factor packaging solution to protect the electronics in the body. In this work, we investigate two promising encapsulation coatings based on thin-film technology as the main packaging for LCP-based electronics. Specifically, a HfO₂–based nanolaminate ceramic (TFE1) deposited via atomic layer deposition (ALD), and a hybrid Parylene C-ALD multilayer stack (TFE2), both with a silicone finish, were investigated and compared to a reference LCP coating. T-peel, water-vapour transmission rate (WVTR) and long-term electrochemical impedance spectrometry (EIS) tests were performed to evaluate adhesion, barrier properties and overall encapsulation performance of the coatings. Both TFE materials showed stable impedance characteristics while submerged in 60 °C saline, with TFE1-silicone lasting more than 16 months under a continuous 14V DC bias (experiment is ongoing). The results presented in this work show that WVTR is not the main factor in determining lifetime, but the adhesion of the coating to the substrate materials plays a key role in maintaining a stable interface and thus longer lifetimes.

In the last years, the increasing demand for ever higher data rates in wireless communication has exposed the limits of current sub-6 GHz communication systems and pushed the technology towards the exploration of the mmWave frequency spectrum. In particular, 3 frequency bands have been licensed at 26 GHz, 28 GHz and 39 GHz for the new generation of mobile communication (5G), each exhibiting as much as 3 GHz of operational bandwidth. However, systems operating at mmWave have to cope with much higher free space losses then in the sub-6 GHz frequency range. Moreover, the physical size of interconnects (chip-to-chip, chip-to-antenna) becomes comparable to the operating wavelength. Therefore, new packaging technologies are required, which allow implementing large antenna arrays for massive MIMO and short interconnects to minimize package losses. Within the funded project IPCEI “mmWave Modules” a scalable and reconfigurable module for mmWave 5G small cell base stations has been developed. In particular, the module measures and exhibits two dual-band patch antenna arrays for operation at 28 GHz and 39 GHz. Moreover, it may be easily upscaled for the deployment in base stations covering larger cells. Packaging technology is based on a double molded Fan-out Wafer Level Package (FOWLP) approach with integrated antenna-in-package (AiP) that has been adapted and evaluated. The Analog-Front-End-IC (AFE IC) has been packaged as a start in an RDLfirst FOWLP on 300 mm wafer size. Redistribution layers were built-up on a glass carrier consequently followed by plating of the through package vias [TPVs] for later front and backside package connection. The AFE IC is then assembled as a flip chip on the RDL and compression molding is used to underfill the flip chip ICs and overmold the wafer carrier in one step. A backgrinding step is applied to open the TPVs for further electrical connection. Direct metallization using seed layer sputtering, copper plating and subtractive etching is used to add a shielding layer on the mold cap. After debonding the wafer is overmolded a second time using compression molding again. The antenna is then directly metallized on the second mold cap connected by laser drilled and metallized vias to TPVs and shielding layer. Finally solder balls are attached and packages are separated by dicing. Focus of the development was the double mold process with the related warpage challenges, direct metallization on mold as well as antenna and via integration and alignment on the second mold layer. Besides the development of the entire package the AiP concept has been evaluated using a GHz/39 GHz dual-band antenna test structure considering the later double mold approach including an inner shielding layer, laser drilled through mold vias and direct metallized antenna on mold. Measured bandwidths of 1 GHz and 700 MHz and gains of 5.3 dBi and 6.2 dBi at 28 GHz and 39 GHz, respectively, prove the applicability of the proposed packaging technology for mmWave 5G applications. In summary the paper will describe the FOWLP package development for a mmWave 5G MIMO application with focus on a double mold approach with antenna-in-package application.