A mixer-first receiver frontend with resistive-feedback baseband is proposed. The baseband combination of G m and transimpedance amplifier (TIA) is designed to cover a wide frequency range for high data rate applications. The N-path filtering at the RF side and enhanced filtering at the BB side inhibit out-of-band blocker interferences. The receiver is fabricated in a 65 nm CMOS. Measurement results display an NF of 2.3 dB and a conversion gain of 33.5 dB at 2 GHz f LO . The in-band and out-of-band IIP3 are −7.5 dBm and 19 dBm respectively. The receiver core draws 34 mW in the signal path and occupies an active area of 0.31 mm ² .

A CMOS baseband‐active‐feedback receiver frontend with passive voltage‐commutating mixers is proposed. The active feedback baseband enables in‐band signal amplification and out‐of‐band blocker interference suppression by constructing the RF bandpass filter and BB lowpass filter, simultaneously. The voltage‐commutating mixers embedded in current mirrors significantly reduce the power requirement for the LO generator. The stacked n/pMOS structure is commonly adopted to further improve power efficiency. The receiver frontend is designed in a standard 65 nm CMOS process. Simulation results display an NF of 3.4 dB and a maximum gain of 32 dB from 1 to 5 GHz LO frequency range. The obtained in‐band and out‐of‐band IIP3 are −12 dBm and 9 dBm, respectively. The receiver frontend core only consumes 22 mW at 1 GHz LO frequency and occupies the area of 645 × 543 μm ² , which is suitable for the low‐power application of handheld terminals.

In this paper, by using the baseband noise cancellation, a CMOS mixer-first analog receiver with power reduction is proposed. Based on a current-mirror transimpedance amplifier structure, positive capacitive feedback is applied to manipulate poles/zeros location, enabling a wide baseband bandwidth and out-of-band second-order filtering profile. The additional radio frequency N-path filtering and baseband 40dB/dec roll-off absorb out-of-band interferences. The presented receiver frontend is fabricated in a standard 65 nm CMOS process. Measured results demonstrate a minimal noise figure of 2.2 dB, and an average voltage gain of 32.2 dB across the 220 MHz intermediate frequency range. The in-band and out-of-band third-order input intercept point manifests -12.8 dBm and 15.5 dBm respectively. The presented receiver circuit draws ~32 mW at a typical 1 GHz local oscillator stimulus.

Metal–organic framework (MOF) material is one of the most promising porous nanomaterials for volatile organic compound (VOC) adsorption and sensing. The large surface area and the high porosity of MOF contribute to the high sensitivity of MOF-based VOC sensors. In this study, we engineer the coating of the zeolitic imidazolate framework material ZIF-8 grown on the surface of a long-period fiber grating (LPFG) for acetone vapor sensing. Being a periodic structure formed in a single-mode optical fiber, an LPFG is designed to couple light from the core to the cladding of the fiber at a specific resonance wavelength. Adsorption of acetone vapor molecules in the framework of the ZIF-8 coating can change the refractive index of the coating and cause a shift in the resonance wavelength of the LPFG. The sensitivity of the resonance shift of the LPFG to the acetone vapor concentration depends strongly on the thickness of the ZIF-8 coating. To create a dense ZIF-8 coating, at least five growth cycles of ZIF-8 (30 min growth for one cycle) are required, and nine growth cycles can create a 500 nm thick coating. The LPFG coated with nine growth cycles of ZIF-8 provides a high sensitivity of 21.9 nm ppm⁻¹, a low detection limit of 1.4 ppm, and a wide detection range of about 1500 ppm. Our results can facilitate the development of high-performance optical fiber sensors based on MOF for VOC detection.

In this paper, a 0.18 μm n-type LDMOS is researched. By optimized manufacture process and device structures, ultra-low specific on resistance (Ronsp) is achieved. Pbody and n-type drift region are all full self-aligned implantation (FSAI). For different structures, the uniformities of the DC parameters affected by the process variation are researched. Experimental results show that: by optimizing manufacture process and device structures, the FSAI nLDMOS has competitive Ronsp compared with other technologies. For Breakdown voltage equals to 42 V and 52 V, the Ronsp are 18.7 mΩ•mm2 and 30 mΩ•mm2 respectively. For FSAI-nLDMOS, both simulation and experiment demonstrated that the shift of the DC parameters generated by the process variation is superior to the other technologies. Moreover, only one n-type drift region with filed oxide is used. The device is fabricated in bulk-silicon without epitaxy. These leads to the low cost of the fabrication.