Computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

A piezoelectric ultrasonic transducer (PUT) is widely used in nondestructive testing, medical imaging, and particle manipulation, etc., and the performance of the PUT determines its functional performance and effectiveness in these applications. The optimization design method of a PUT is very important for the fabrication of a high-performance PUT. In this paper, traditional and efficient optimization design methods for a PUT are presented. The traditional optimization design methods are mainly based on an analytical model, an equivalent circuit model, or a finite element model and the design parameters are adjusted by a trial-and-error method, which relies on the experience of experts and has a relatively low efficiency. Recently, by combining intelligent optimization algorithms, efficient optimization design methods for a PUT have been developed based on a traditional model or a data-driven model, which can effectively improve the design efficiency of a PUT and reduce its development cycle and cost. The advantages and disadvantages of the presented methods are compared and discussed. Finally, the optimization design methods for PUT are concluded, and their future perspectives are discussed.

The miniaturized and low-cost reconfigurable transceivers show promising prospects in brain-machine interfaces, implantable devices, and wearable devices. As basic elements of transceivers, further improvement of tuning range, operating frequency, and area of tunable inductors are extremely needed. In this work, a magnetic coupling ultrawide range inductors tuning technique is proposed and analyzed with the process-based coupling circuit model. The model simulation and test chip verification results are in good agreement. From dc to 30 GHz, an inductance value of 0.04–10.32 nH (self-inductance is 1.03 nH), a tuning range of 99.61%, and a quality factor (Q) of 145.6 are achieved. This indicates that a 10.02-fold increase in inductance value can be obtained without increasing the chip area compared to a fixed inductor with an area of $95 \times 130 \, \mu $ m. The tuning technique and model can be employed for the design of tunable matching networks and filters to further improve the integration of reconfigurable radio frequency (RF) transceivers.

A bandwidth optimization model for a novel equivalent 90° transmission-line section is proposed in this paper. Furthermore, the structure of 3-D compact 3-dB branch-line directional coupler and its equivalent-circuit model are presented. They can achieve both excellent isolations between each branch and high-density integration by using equivalent 90° transmission-line sections and coaxial through-silicon via technology in 3-D integrated circuits. Finally, a 3-D coupler is designed with the center frequency of 100 GHz, as well as the bandwidth and size reach 20 GHz and 174 × 236.9 × 208.7 μm ³ , respectively. The results of the 3-D full-wave field solver High-Frequency Structure Simulator and the proposed model are well matched, showing that the proposed model can be used to quickly evaluate the electrical performance of the 3-D coupler before manufacture, thus effectively promoting the design efficiency and quality.

Microsystems are widely used in 5G, the Internet of Things, smart electronic devices and other fields, and signal integrity (SI) determines their performance. Establishing accurate and fast predictive models and intelligent optimization models for SI in microsystems is extremely essential. Recently, neural networks (NNs) and heuristic optimization algorithms have been widely used to predict the SI performance of microsystems. This paper systematically summarizes the neural network methods applied in the prediction of microsystem SI performance, including artificial neural network (ANN), deep neural network (DNN), recurrent neural network (RNN), convolutional neural network (CNN), etc., as well as intelligent algorithms applied in the optimization of microsystem SI, including genetic algorithm (GA), differential evolution (DE), deep partition tree Bayesian optimization (DPTBO), two stage Bayesian optimization (TSBO), etc., and compares and discusses the characteristics and application fields of the current applied methods. The future development prospects are also predicted. Finally, the article is summarized.

In this article, an intelligent multifield collaborative optimization method of a through silicon via (TSV) array with performance constraints is proposed. The multiphysical field-coupled cosimulation of the TSV array is carried out using COMSOL and ANSYS, and the effects of design parameters (radius, oxide thickness, pitch, offset angle, and height) on the performance (electrical, thermal, stress, and area) of the TSV array are analyzed. The mapping relationship between the design and performance parameters is established by a neural network. A collaborative optimization strategy with performance constraints is proposed, and the design parameters are optimized by a particle swarm optimization (PSO) algorithm. According to the optimized design parameters, the simulation results of the finite-element method (FEM) are basically consistent with the predicted performance. The maximum deviation between simulation verification and optimization results is 3.04%, and the proposed method reduces the search time by 99.52% and computation time by 83.86% compared to traditional methods, respectively.