In 3-D NAND flash memory, the channel is always offset due to the complicated interference from the program/erase (PE), including the data retention and layer interference, so that the channel estimation is desired. However, due to the physical structure of 3-D flash memory, there exists significant variation in channel parameters and inconsistent channel offsets among different wordlines. As a result, the process of estimating channel parameters for each individual wordline typically requires a considerable amount of computational resources, resulting in the high latency of system, which becomes a new challenge. To tackle this problem, two unsupervised learning algorithms are proposed to estimate the channel parameters, based on analyzing the error distribution in 3-D flash memory. To address the longer read latency introduced by the unsupervised learning algorithm for the channel estimation, we further propose a low-latency detection algorithm, which first detects whether the current channel needs to be updated. In the event that an update is required, the algorithm only periodically estimates the channel parameters during system idle times, resulting in a more efficient and streamlined process. Compared to the existing methods, the proposed algorithms can efficiently estimate channel parameters with lower-computational complexity. Moreover, combining with the search algorithm, a correction scheme is proposed to minimize the error between the estimated read reference voltage (RRV) and the optimal RRV in the actual device. Theoretical analysis and simulation results demonstrate that the proposed method can improve the lifetime of flash memory and reduces the number of read retries.

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

As high-speed big-data communications impose new requirements on storage latency, low-density parity-check (LDPC) codes have become a widely used technology in flash-memory channels. However, the iterative LDPC decoding algorithm faces a high decoding latency problem due to its mechanism based on iterative message transmission. Motivated by the unbalanced bit reliability of codeword, this paper proposes two technologies, i.e., serial entropy feature-based layered normalized min-sum (S-EFB-LNMS) decoding and parallel entropy feature-based layered normalized min-sum (P-EFB-LNMS) decoding. First, we construct an entropy feature vector that reflects the real-time bit reliability of the codeword. Then, the reliability of the output information of the layered processing unit (LPU) is evaluated by analyzing the similarity between the check matrix and the entropy feature vector. Based on this evaluation, we can dynamically allocate and schedule LPUs during the decoding iteration process, thereby optimizing the entire decoding process. Experimental results show that these techniques can significantly reduce decoding latency.