Chang Liu

Dr. Chang Liu


Research Focus & Metrics

Academic Career Length

13Years (2014-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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5 January 2023 in IEEE Transactions on Vehicular Technology
Verified
Journal Article
Closed access
ZXZheng Xue
Zheng Xue
CLChang Liu
Chang Liu
CLCanliang Liao
Canliang Liao
GHGUOJUN HAN
GUOJUN HAN
ZSZhengguo Sheng
Zhengguo Sheng
Vehicular edge computing (VEC) is a new computing paradigm that enhances vehicular performance by introducing both computation offloading and service caching, to resource-constrained vehicles and ubiquitous edge servers. Recent developments of autonomous vehicles enable a variety of applications that demand high computing resources and low latency, such as automatic driving, auto navigation, etc. However, the highly dynamic topology of vehicular networks and limited caching space at resource-constrained edge servers calls for intelligent design of caching placement and computation offloading. Meanwhile, service caching decisions are highly correlated to the computation offloading decisions, which pose a great challenge to effectively design service caching and computation offloading strategies. In this paper, we investigate a joint optimization problem by integrating service caching and computation offloading in a general VEC scenario with time-varying task requests. To minimize the average task processing delay, we formulate the problem using long-term mixed integer non-linear programming (MINLP) and propose an algorithm based on deep reinforcement learning to obtain a suboptimal solution with low computation complexity. The simulation results demonstrate that our proposed scheme exhibits an effective performance improvement in task processing delay compared with other representative benchmark methods.

11 October 2022 in IEEE Transactions on Consumer Electronics
Verified
Journal Article
Closed access
YLYingge Li
Yingge Li
GHGUOJUN HAN
GUOJUN HAN
SHSanwei Huang
Sanwei Huang
CLChang Liu
Chang Liu
MZMeng Zhang
Meng Zhang
FWFei Wu
Fei Wu
In consumer electronics, 3-D NAND flash memory has become the state-of-the-art storage medium due to the multi-bit storage per cell and 3-D stacking technology. However, flash memory cells are commonly vulnerable to numerous types of circuit-level noise, resulting in threshold voltage distribution distortion and decreased reliability. Characterization of the threshold voltage distribution and modeling of optimal read reference voltages can help to mitigate the reliability deterioration. We provide a solution for improving the reliability of flash memories while reducing their implementation cost in this paper. The proposed pre-processing method is shown to yield a smaller number of scanning voltage steps reducing the time overhead and energy consumption of multiple read operations during the characterization of threshold voltage distributions. We propose a single state asynchronous estimation (SSAE) method to estimate optimal read reference voltages. Compared with the advanced two-state asynchronous estimation (TSAE) method, it is shown to reduce the computational and space overhead by half. Furthermore, compared with using the default read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.

17 September 2024 in IEEE Internet of Things Journal
Verified
Journal Article
Closed access
CLChang Liu
Chang Liu
ZXZheng Xue
Zheng Xue
CLCanliang Liao
Canliang Liao
JKJiawen Kang
Jiawen Kang
GHGUOJUN HAN
GUOJUN HAN
Edge caching is crucial for enhancing the performance of vehicular networks primarily by reducing service latency and improving data availability. However, existing research typically focuses only on unidirectional vehicle movement, which limits its application in complex scenarios, such as those in urban areas. To address this, we propose two novel edge caching strategies specifically tailored for the intricate vehicle movements and traffic signal controls at urban intersections, taking into account temporal variability of content popularity, making them more practical in the real world. The first caching strategy, based on dynamic programming (DP), is suited for scenarios with low traffic flow, providing an optimal solution and serving as a benchmark for evaluating the performance of the second strategy. This benchmark assesses how closely the second strategy approaches the optimal solution. The second strategy employs deep reinforcement learning (DRL) and is suitable for high traffic scenarios. Its performance, when compared with the DP approach in low traffic scenarios, demonstrates results that are near-optimal. Simulation outcomes indicate that the DRL strategy effectively adapts to changes in content popularity, significantly optimizing service latency and hit rates.

24 July 2020 in IEEE Open Journal of the Communications Society
Verified
Journal Article
Open access
CLChang Liu
Chang Liu
ZHZygmunt J. Haas
Zygmunt J. Haas
ZTZijing Tian
Zijing Tian
Recently, tag-to-tag (T2T) backscattering technique in a passive RFID system has received broad attention due to its superiority for large-scale network applications. If used to implement a Network of Tags, use of T2T communication allows inherent communication parallelism, thus supporting orders of magnitude larger capacity than centralized RFID reader-based systems. To unleash the potential of T2T communication, turbo backscattering operation enables the implementation of a multi-hop network of tags, which supports larger network coverage of a Network of Tags. However, due to asymmetric communication links and interferences among tags’ transmissions in such a T2T backscattering based network, the routing protocol design has become one of the main technical challenges, especially for large-scale networks. Furthermore, the computation time of T2T routing protocols increases exponentially with the number of tags, greatly limiting the practicability of such large-scale backscattering networks. In this paper, we present the design of a Network of Tags model to address these challenges, and we propose novel routing protocols for three distinct types of tags with different hardware capabilities. To address the issue of computational processing time of the routing protocol for large-scale T2T networks, we propose a new scheme with linear time complexity. We evaluate and compare the performance of the proposed protocols, as well as investigate the impact of network parameters on the performance.

8 July 2025 in IEEE Transactions on Vehicular Technology
Verified
Journal Article
Closed access
ZXZheng Xue
Zheng Xue
CLChang Liu
Chang Liu
FWFuxi Wen
Fuxi Wen
GHGUOJUN HAN
GUOJUN HAN
Vehicular edge computing (VEC) is a promising technology for networked autonomous driving. It not only enhances task offloading and computation for autonomous vehicles, but also expands their perception range and significantly reduces computational costs. Current research primarily focuses on resource allocation for single-vehicle perception task offloading, while cooperative perception tasks have the potential to resolve challenges such as occlusion and sensing range limitations. The phased and composite nature of these tasks introduces specific, yet unmet, design requirements for resource allocation schemes. To address these challenges, this paper develops a novel multi-stage task offloading and resource allocation framework that accounts for the phased structure of collaborative perception tasks and the heterogeneous computational capabilities of vehicles. We introduce a dynamic task-service model for tasks within regions of interest (RoI), and formulate the joint offloading and resource allocation problem as a mixed-integer nonlinear program (MINLP) to minimize task completion latency. An optimal scheme is then proposed, covering task execution, node selection, and resource allocation to enable adaptive and fine-grained collaboration. Numerical results, when compared with existing benchmark algorithms, indicate that our method achieves substantial improvements, reducing latency by an average of 10.5%.

19 July 2023 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
YLYingge Li
Yingge Li
GHGUOJUN HAN
GUOJUN HAN
CLChang Liu
Chang Liu
MZMeng Zhang
Meng Zhang
FWFei Wu
Fei Wu
Low-density parity-check (LDPC) codes have been widely adopted to guarantee data reliability in 3-D NAND flash memory. However, the iterative LDPC decoding algorithm leads to high decoding latency due to the iterative message transfer mechanism. Using a field-programmable gate array (FPGA) testbed, we first present the binary channel in NAND flash and analyze the single-symbol log-likelihood ratio (LLR) variation with the decoding iterations. Subsequently, we investigate the raw bit error ratio (RBER) characteristics of intra-page frames. To reduce the number of iterative decoding, we propose a frame feedback information aware decoding algorithm (FFIA-DA), combined with the single-symbol LLR variation and the similar error characteristics among intra-page frames. The proposed method uses the decoding feedback information of one frame to decrease the number of decoding iterations of other frames with similar RBER. Experiments show that the proposed approach can improve the decoding performance of LDPC and speed up decoding convergence.