A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm ² of total silicon area, lowering the area by $3.22\times $ times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with $1.25~\mu V_{\mathrm {RMS}}$ input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR.

Quantization-induced limit cycle oscillations (LCOs) in digitally controlled DC-DC converters are addressed in this paper. The novel Dyadic Digital PWM (DDPWM) is proposed to increase the effective pulse-width-modulator (PWM) resolution, as required for LCO-free operation, at low cost, without sacrificing DC accuracy and with no detrimental effects on the ripple voltage. Experimental results on a synchronous buck validate the approach highlighting effective LCOs suppression and DC accuracy enhancement at 5X reduced peak output voltage ripple and up to 16dB lower-frequency harmonic component reduction compared to thermometric dithering for the same resolution increase.

In this paper, the effects of electromagnetic interference (EMI) coupled to a radio-frequency (RF) communication channel by resonant mechanisms are investigated and described in the framework of Shannon information theory in terms of an equivalent channel capacity loss so that to analyze and compare the effects of non-modulated and random Spread Spectrum (SS) modulated EMI. The analysis reveals a higher EMI-induced capacity loss for SS-modulated compared to non modulated EMI under practical values of the quality factor Q, while a modest improvement in the worst case capacity loss is observed only for impractical values of Q. Simulations on a 4-quadrature amplitude modulation (4-QAM) digital link featuring Turbo coding under EMI resonant coupling reveal that SS-modulated EMI gives rise to higher bit error rate (BER) at lower EMI power compared non-modulated EMI in the presence of resonant coupling for practical values of Q, thus suggesting a worse interfering potential of SS-modulated EMI.

This work presents a new methodology to derive the equivalent circuit of the parasitic paths that propagate switching noise in mixed-signals integrated circuits and that usually lead to unintended crosstalk and electromagnetic emission issues. The methodology is based on small-signal analyses performed at the individual analog and digital microcontroller building block level, on electromagnetic simulations carried out to describe the power supply network at the chip- and at the package-level and on the analysis of the chip layout and process technology data to model the parasitic coupling paths through the semiconductor substrate. The electrical model of microcontrollers generated according to this methodology, consists of a low-complex and linear netlist that provides insight regarding the relationships between the design parameters and noise propagation paths in the early design phases, through simulations in a SPICE-like environment. The proposed approach does not rely on experimental test results. In this paper, the electric model of an 8 bit microcontroller, which validity has been proved by scattering parameter and conducted emission measurements, is derived.

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514,S/s prototype (ReDAC1) and on a 11-bit, 10.5,kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68,LSB (1.53,LSB) maximum INL, 1.54,LSB (1.0,LSB) maximum DNL, 76.4,dB (67.9,dB) THD, 79.7,dB (71.4,dB) SFDR and 71.3,dB (63.3,dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB).