A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process. In comparison to other fully-integrated designs, the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 μA to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than -12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures 260×90 μm ² , including 140 pF of stacked on-chip capacitors.

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |V _AC |. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm ² . For the proposed rectifier measured at |V _AC | = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for R _L =500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |V _AC | ranges from 1.5 to 4 V for R _L =500 Ω.

This paper presents a fully-integrated flipped-voltage-follower (FVF) based low-dropout (LDO) regulator with enhanced full-spectrum power supply rejection (PSR) and unity-gain bandwidth (UGB) over 400MHz for noise-sensitive circuits. Following the study of three types of FVF LDO's PSR performances, we propose a novel FVF LDO with a low-gain fast loop-1 and a high-gain slow loop-2. In prior FVF LDOs, their PSRs are either full-spectrum, or not, but with low PSR at low frequency. In this work, we fully utilize both DC gains of loop-1 and loop-2 for the low-frequency PSR, while the high-frequency PSR remains unchanged. In addition, we use dynamic compensation to push the loop-2's UGB to higher frequency for a better PSR bandwidth. This work, fabricated in 65 nm CMOS, with 1.2-V input and 1-V output, exhibits a measured quiescent current (IQ) varying from 27 to 82μA for a load current ILOAD between 5μA and 20mA. The circuit achieves a low frequency PSR of μ 58dB with the worst full-spectrum PSR of μ9dB in 20mA ILOAD with a 300pF on-chip output capacitor. Further, with an UGB over 400MHz, the proposed FVF LDO reaches 0.9ns response time when ILOAD changes between 100μA and 20mA with edge times less than 0.8ns.

This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control. For responding to instant load transients, the proposed high-pass AA loop momentarily adjusts the unit current of the power switch array, and significantly reduces the voltage spikes. In the proposed D-LDO, the overall 512 output current steps are divided into three sub-sections controlled by coarse/fine loops with carry-in/out operations. Therefore, the required shift register (SR) length is reduced, and a 9-bit output current resolution is realized by using only 28-SR bits. Besides, the coarse-tuning loop helps to reduce the recovery time, while the fine-tuning loop improves the output accuracy. To eliminate the limit cycle oscillation and reduce the quiescent current, a freeze mode is added after the fine-tuning operation. To reduce the output glitches and the recovery time, a nonlinear coarse word control is designed for the carry-in/out operations. The D-LDO is fabricated in a 65-nm general purpose CMOS process. A maximum voltage undershoot/overshoot of 105 mV is measured with a 10-mA/1-ns load step and a total capacitor of only 100 pF. Thus, the resulting figure-of-merit is 0.23 ps.

An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm ² . The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current.

Battery-to-battery (B2B) wireless charging can take place in many scenarios, such as using a mobile phone to charge another mobile phone, wearable devices, or low-power sensor nodes. To facilitate this wireless power transfer (WPT) function with the minimum additional cost, we propose a monolithic reconfigurable bidirectional WPT transceiver designed for the first time in CMOS, which can be reconfigured between a differential class-D power amplifier (PA) and a full-wave rectifier. Meanwhile, we employed a maximum current charging mode to maximize the B2B charging efficiency, by directly charging the loading battery with the rectifier, and by powering the PA with the sourcing battery. Then, we reduced the number of cascaded WPT stages from five in the conventional design to three. This bidirectional WPT transceiver fabricated in 0.35 μm CMOS occupies 3.9 mm ² of silicon area. The bidirectional WPT function, verified at 6.78 MHz with only one off-chip capacitor, exhibits peak efficiencies of 91.5% and 58.6% for the receiver and the overall system, respectively, when the output power is 1.55 W.