本論文主要分為三個主題。第一個主題為實現圈數比為1：n同時保有高耦合係數之堆疊變壓器。以往堆疊變壓器在圈數比為1：1的結構下，耦合係數可達到0.9，但在非1：1的圈數比下，就無法達到較高的耦合係數，因此，我們使用雙圈堆疊變壓器結構，並利用多層金屬層的佈局方式，設計六個面積不同的堆疊變壓器並分為兩組，兩組變壓器之圈數比分別約為1.59與1.9，最後量測出之耦合係數分別為0.955與0.89。實驗結果顯示出有別於以往的高耦合係數堆疊變壓器，只能在圈數比為1：1的結構下才有高耦合係數，本文之堆疊變壓器在圈數比為1：n的情況下也可得到高耦合係數。在實現圈數比1：n高耦合係數變壓器後，本文將對變壓器的面積效應進行分析，本文設計六個不同面積大小之堆疊變壓器，最後將選出有最佳佈局參數的變壓器。第二個主題為可變寬度堆疊變壓器的實現。利用本實驗室指導教授許恆銘教授以及曾建文學長發表之阻值最佳化方式，套用至對稱型堆疊變壓器以及堆疊型變壓器兩種不同結構的變壓器上，此阻值最佳化方法可降低變壓器的繞線電阻，使其在同樣自感值下，能較固定寬度變壓器有著更高的Q值，改善幅度達10％，進而提升變壓器特徵阻抗，且不會影響到耦合係數。第一、第二個主題所有的堆疊型變壓器皆使用90nm的製程實現，並證明其在高頻時的效能改善。¬第三個主題為利用變壓器之電壓控制振盪器(VCO)，本電壓控制振盪器最高操作頻率為2.4GHz，使用變壓器取代電感，與可變電容並聯做為電壓控制振盪器的諧振電路，可降低相位雜訊，最後量測結果為在2.4GHz時的相位雜訊為-87.6dBc/Hz，在2.17GHz時為-117dBc/Hz，可調範圍為200MHz。本電壓控制振盪器以TSMC 0.18μm實現。This thesis includes three topics, the first topic is to realize a stacked transformer has both different turn ratio and high coupling factor simultaneously. In report literature, the turn ratio of transformer is 1:1 and the coupling factor is 0.9. Generally, the turn ratio changes from 1:1 to 1:n, the resulted transformer can''t reach the high coupling factor. Accordingly, the stacked transformer with 2-turned is proposed in this thesis. In this work, we design six stacked transformers, and then divide them into two groups with different turn ratio: 1.59 and 1.9. Measurement results show that coupling factor of two groups achieves value of 0.955 and 0.89, respectively. According to previous report, the 1:1 stacked transformer could reach higher coupling factor than 1:n stacked transformer. However, the experiment indicates that the 1:n stacked transformers could have perfect coupling factor performance. Secondly, the investigation on the chip area effect is addressed in these transformers, and then the optimization layout among the six 2-turned stacked transformers. The corresponding topic is to realize a variable widths stacked transformers. When transformers utilize variable widths, it could reduce coil resistance, improve the Q factor about 10％ and transformer efficiency compare to a fixed width transformer. Finally, we proposed a 2.4GHz voltage control oscillator (VCO) using transformer. The proposed VCO replace the inductor by using the transformer in the L-C tank, due to characteristic of reduced phase noise, the VCO was fabricated in a TSMC 0.18μm CMOS technology. Measurement result shows that the -117dBc/Hz of the phase noise of the VCO at 2.17GHz and 200MHz of the tuning range.誌謝 Ⅰ 摘要 Ⅱ ABSTRACT Ⅲ 目錄 Ⅳ 表目錄 Ⅵ 圖目錄 Ⅶ 第一章 緒論 1 1-1 動機 1 1-2 文獻回顧 1 1-3 論文架構 2 第二章 1:N堆疊型變壓器 3 2-1 變壓器參數 3 2-1-1 耦合係數K 3 2-1-2 圈數比n 4 2-1-3 變壓器等效電路參數 5 2-2 品質因素 6 2-3 TCR(TRANSFORMER CHARACTERISTIC RESISTANCE) 8 2-4 KELVIN 4點探針直流量測方法 9 2-5 實驗設計 10 2-5-1 堆疊型變壓器結構 10 2-5-2 實驗結果與量測分析 14 2-5-3 等效電路模型： 28 第三章 可變寬度變壓器 44 3-1 可變寬度理論 44 3-2 可變寬度對稱型變壓器 45 3-2-1 實驗設計 45 3-2-2 可變寬度對稱型變壓器結構說明： 45 3-2-3 實驗結果與量測分析 47 3-2-4 等效電路模型： 59 3-3 可變寬度堆疊型變壓器 64 3-3-1 實驗設計 64 3-3-2 結構說明 64 3-3-3 實驗結果與量測分析 67 第四章 電壓控制震盪器 81 4-1 電壓控制震盪器 81 4-1-1 電壓控制震盪器原理 81 4-1-1-1 IEEE 802.11 射頻系統規範 81 4-1-1-2 類比回授觀點 83 4-1-1-3 高頻負電阻觀點 84 4-1-1-4相位雜訊 87 4-1-1-5 相位雜訊的定義 87 4-2 實驗電路結構 89 4-2-1 諧振電路 89 4-2-2 變壓器 91 4-2-3 實驗架構 94 4-2-4 量測結果 95 第五章 結論與未來工作目標 97 5-1 結論 97 5-2 未來工作 97 參考文獻 98 表目錄 表2-1 TR1~TR6佈局參數 14 表2-2 TR1~TR3寄生電容值 15 表2-3 K與導線長度距離比關係 16 表2-4 TR1~TR3 SQUARE NUMBER/T比較表 18 表2-4-1 TR1~TR3導電係數 18 表2-5 TR4~TR6寄生電容值 22 表2-6 SQUARE NUMBER比較表 23 表2-6-1 TR4~TR6導電係數 23 表2-7 量測數據 27 表2-8 等效電路參數值 36 表2-9 TR4~TR6等效電路參數值 43 表3-1 佈局參數 47 表3-2 CA1、CA2 一、二次側SQUARE NUMBER 51 表3-4 K值與L/D的關係 58 表3-5 量測結果 58 表3-6 等效電路參數值 64 表3-7 佈局參數表 67 表3-8 CC1、CC2內外圈總SQUARE NUMBER比較 71 表3-9 CE1、CE2線段總SQUARE NUMBER比較 76 表3-10 量測結果 80 表 3-11 K值與L/D的關係 80 表4-1 802.11規格表 82 表4-2 變壓器佈局參數 91 表4-3 變壓器模擬參數 93 表4-4 模擬參數與量測數據比較 96 圖目錄 圖2-1 理想變壓器 3 圖2-2 變壓器等效電路圖 5...

This paper presents a compact model of mutual inductance between two planar inductors, which is essential to design and optimize a wireless power transmission system. The tracks of the planar inductors are modeled as constant current carrying filaments, and the mutual inductance between individual filaments is determined by Neumann's integral. The proposed model is derived by solving Neumann's integral using a series expansion technique. This model can predict the mutual inductance at various axial and lateral displacements. Mutual coupling between planar inductors is computed by a 3-D electromagnetic (EM) solver, and the proposed model shows good agreement with these numerical results. Different types of planar inductors were fabricated on a printed circuit board (PCB) or silicon wafer. Using these inductors, wireless power links were constructed for applications like implantable biomedical devices and contactless battery charging systems. Mutual inductance was measured for each of the cases, and the comparison shows that the proposed model can predict mutual coupling suitably.

A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process. In comparison to other fully-integrated designs, the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 μA to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than -12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures 260×90 μm ² , including 140 pF of stacked on-chip capacitors.

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).