This brief presents a dual-path CMOS rectifier with adaptive control for ultrahigh-frequency (UHF) RF energy harvesters. The input power range with high power conversion efficiency (high PCE) of the rectifier is extended by the proposed architecture, which includes a low-power path and a high-power path. The dual-path rectifier with an adaptive control circuit is fabricated in a 65-nm CMOS process. Operating at 900 MHz and driving a 147-kΩ load resistor, the measured PCE of this work can be maintained above 20% with an 11-dB input range from -16 to -5 dBm, while only an 8-dB input range can be achieved with traditional single-path rectifiers. A sensitivity of -17.7 dBm is measured with 1-V output voltage across a capacitive load.

The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. However, the tradeoff between current efficiency and transient response speed has limited its applications. In this brief, a coarse-fine-tuning technique with burst-mode operation is proposed to the D-LDO. Once the voltage undershoot/ overshoot is detected, the coarse tuning quickly finds out the coarse control word in which the load current should be located, with large power MOS strength and high sampling frequency for a fixed time. Then, the fine-tuning, with reduced power MOS strength and sampling frequency, regulates the D-LDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. The proposed D-LDO is verified in a 65-nm CMOS process with a 0.01-mm ² active area. The measured voltage undershoot and overshoot are 55 and 47 mV, respectively, with load steps of 2 to 100 mA with a 20-ns edge time. The quiescent current is 82 μA, with a 0.43-ps figure of merit achieved. Moreover, the reference tracking speed is 1.5 V/μs.

This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control. For responding to instant load transients, the proposed high-pass AA loop momentarily adjusts the unit current of the power switch array, and significantly reduces the voltage spikes. In the proposed D-LDO, the overall 512 output current steps are divided into three sub-sections controlled by coarse/fine loops with carry-in/out operations. Therefore, the required shift register (SR) length is reduced, and a 9-bit output current resolution is realized by using only 28-SR bits. Besides, the coarse-tuning loop helps to reduce the recovery time, while the fine-tuning loop improves the output accuracy. To eliminate the limit cycle oscillation and reduce the quiescent current, a freeze mode is added after the fine-tuning operation. To reduce the output glitches and the recovery time, a nonlinear coarse word control is designed for the carry-in/out operations. The D-LDO is fabricated in a 65-nm general purpose CMOS process. A maximum voltage undershoot/overshoot of 105 mV is measured with a 10-mA/1-ns load step and a total capacitor of only 100 pF. Thus, the resulting figure-of-merit is 0.23 ps.

Battery-to-battery (B2B) wireless charging can take place in many scenarios, such as using a mobile phone to charge another mobile phone, wearable devices, or low-power sensor nodes. To facilitate this wireless power transfer (WPT) function with the minimum additional cost, we propose a monolithic reconfigurable bidirectional WPT transceiver designed for the first time in CMOS, which can be reconfigured between a differential class-D power amplifier (PA) and a full-wave rectifier. Meanwhile, we employed a maximum current charging mode to maximize the B2B charging efficiency, by directly charging the loading battery with the rectifier, and by powering the PA with the sourcing battery. Then, we reduced the number of cascaded WPT stages from five in the conventional design to three. This bidirectional WPT transceiver fabricated in 0.35 μm CMOS occupies 3.9 mm ² of silicon area. The bidirectional WPT function, verified at 6.78 MHz with only one off-chip capacitor, exhibits peak efficiencies of 91.5% and 58.6% for the receiver and the overall system, respectively, when the output power is 1.55 W.

This paper presents an automatic impedance transforming technique to extend the radio frequency rectifier input power range with high conversion efficiency. The rectifier employs two branches of subrectifier, each achieving impedance matching at high and low input power ranges. Then, the two branches are connected by a λ/4 T-junction power divider. With such configuration, the input impedance of the two subrectifiers are transformed automatically, allowing the impedance matching over a wide input power range. In this way, the injected power can be optimally delivered to the subrectifiers, achieving a high efficiency over this wide input power range. This scheme manages to eliminate the power detetor for branch selection and can be applied to both singleand dual-band rectifiers with a reduced design difficulty. For validation, a single-band rectifier working at 915 MHz and a dual-band rectifier at 915/2450 MHz are implemented. Design analysis on the singleand dual-band rectifiers is carried out. The measurement results show that 68% maximum efficiency is achieved for the single-band (915 MHz) rectifier, and the input power range for the efficiency 70% of the peak efficiency is from -5 to 31 dBm. Besides, the dual-band rectifier shows 66% and 58% peak efficiencies at 915 and 2450 MHz, respectively. The input power range is from -6 to 33 dBm for the efficiency 70% of its peak value at 915 MHz, while from 10 to 32 dBm at 2450 MHz. These indicate that the input power range with high efficiency is extended.

In this paper, we propose a compact dual-band impedance matching network (DBIMN) for radio frequency (RF) rectifiers. The DBIMN is achieved with a single-stage T-type network, with only three segments of the transmission line. We investigate the closed-form design equations, as a design guideline of the DBIMN. In addition, we propose the design methodology of the rectifier using the DBIMN. For validation, we design two dual-band rectifiers (0.915 and 2.45 GHz), for different input power levels. The rectifier with high input power level, is designed for a wireless power transmission (WPT) system. With a 12 dBm input power, the measured power conversion efficiencies (PCEs) are 81.7 and 73.1% at the working frequencies. The PCEs becomes 69.2 and 64.1% (at -1 dBm input power) for the low-power input rectifier that can be used in an RF energy harvesting (RF-EH) system. The simulated and measured results match each other well. Compared with previous designs, the proposed designs have advantages in compactness and high efficiency.