Multilevel inverters (MLI) since its inception have caught the attention of researchers for medium and high power application. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 level at the output with three dc voltage sources and eight switches. Three extention of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, results in maximum efficiency of 98.5%. Nearest level control (NLC) pulse width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to shows the feasibility of the proposed MLI topology.

A new triple voltage boosting switched-capacitor multilevel inverter (SCMLI) is presented in this paper. It can produce 13-level output voltage waveform by utilizing 12 switches, three diodes, three capacitors, and one DC source. The capacitor voltages are self-balanced as all the three capacitors present in the circuit are connected across the DC source to charge it to the desired voltage level for several instants in one fundamental cycle. A detailed comparative analysis is carried to show the advantages of the proposed topology in terms of the number of switches, number of capacitors, number of sources, total standing voltage (TSV), and boosting of the converter with the recently published 13-level topologies. The nearest level control (NLC)-based algorithm is used for generating switching signals for the IGBTs present in the circuit. The TSV of the proposed converter is 22. Experimental results are obtained for different loading conditions by using a laboratory hardware prototype to validate the simulation results. The efficiency of the proposed inverter is 97.2% for a 200 watt load.

Multilevel inverters (MLI) are gaining wider popularity owing to their increasing power handling capability and improving power quality output. With an inclining trend towards renewable energy utilization, they find a vital application in wind and solar power generation systems. This article proposes a new multilevel dc–ac inverter. The proposed MLI produces a twenty five level output and offers an inherent capacitor self-balancing capability. The inherent self-balancing eliminates the requirement of auxiliary sensor circuit or capacitors voltage balancing algorithms. Dual asymmetric voltage sources and switched capacitors along with their proper charging/discharging pattern are utilized for the generation of output levels. A voltage gain of 2 and a total standing voltage (TSV) of 10 is achieved though the proposed inverter. In order to realize the merit of the proposed MLI over recently developed topologies, a comparative analysis in terms of system components such as numbers of power electronic switches, gate driver circuits, diodes, and capacitors as well as system parameters such as voltage gain, TSV and power loss is presented. The proposed MLI is developed in the laboratory and is controlled through the digital signal processor TMS320F28379D using nearest level control technique. The experimental results are acquired for different loads and under varying modulation index to validate the feasibility of the proposed inverter.

As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.

An 11-level switched-capacitor multilevel inverter (SCMLI) with 2.5 times boosting feature is presented in this paper. It can produce an 11-level output voltage waveform by utilizing 14 switches, 3 capacitors, 2 diodes, and 1 DC source. Only nine driver circuits are needed as the topology has three pairs of complementary switches and two bidirectional switches. It has inherent capacitor self-balancing property as the capacitors are connected across the DC voltage source during several states within a fundamental cycle to charge the capacitors to the input voltage. A detailed comparison shows the effectiveness of the proposed topology in terms of the number of switches, number of capacitors, number of sources, total standing voltage (TSV), efficiency, and boosting ability with the state-of-art recently proposed circuits. Subsequently, the performance of the proposed SCMLI is validated experimentally utilizing the nearest level control (NLC), a fundamental frequency-based switching technique.

Multilevel converters (MLCs) are extensively used in medium- and high-power applications. Currently, MLCs are also used in grid integration of renewable sources of energy. In this paper a three-phase 11-level MLC topology is investigated which requires a smaller number of active switches compared to similar existing topologies for the same number of levels. In order to eliminate lower order harmonics, selective harmonic elimination (SHE) pulse width modulation technique is used. A projectile target search (PTS) algorithm is used to solve nonlinear SHE equations to determine the optimum values of switching angles to eliminate 5th, 7th, 11th and 13th harmonics from the converter output voltage. The PTS algorithm finds the best value of switching angles for different modulation indices (M) and these values are used in simulating the converter for eliminating lower order harmonics. Total harmonic distortion (THD) analysis is conducted for PTS optimization techniques at different modulation index. Simulation results are verified by hardware-in-the-loop test of the proposed three-phase converter using a Typhoon HIL-402 emulator.