This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 $\mathsf{\mu }$s to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

Radar sensors are utilized in a variety of applications owing to their robust performance in harsh environments with minimal environmental constraints. Target detection is a crucial aspect of utilizing radar sensors. Radar signal processing for target detection entails fast Fourier transform (FFT) and constant false alarm rate (CFAR) operations to determine the distance and relative velocity of the target. However, the computational intensity of FFT and CFAR operations poses challenges for real-time operation. Despite the need for diverse radar specifications across different applications and operating environments, traditional radar signal processors designed for specific uses limit versatility. Therefore, this paper proposes a reconfigurable radar signal processor (R-RSP) comprising FFT and CFAR intellectual property (IP) modules to dynamically accommodate different radar requirements. The FFT IP can support FFT operations on variable-length inputs, ranging from 64-point to 4096-point inputs. Similarly, the CFAR IP supports various algorithms, such as cell averaging (CA) CFAR, ordered statistics (OS) CFAR, smallest of OS (SOOS) CFAR, and greatest of OS (GOOS) CFAR, providing flexibility to select the optimal algorithm for different environments. To validate the R-RSP, we conducted detection experiments involving humans, drones, and cars utilizing a variety of radar sensors. The results demonstrate a minimum acceleration of approximately 16 times and a maximum acceleration of approximately 1,130 times compared to the performance of the ARM Cortex-A53 microprocessor.

The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing memory accesses, execution time, and energy consumption. The embedded NMP module in SARDIMM optionally supports a combination of FFT, IFFT, and matched filter operations of the RDA for range and azimuth compression. The operator within the NMP module accelerates the FFT by performing two radix-2 single butterfly operations in parallel. The NMP module was implemented and validated on a Xilinx UltraScale+ field-programmable gate array (FPGA) using Verilog-HDL. The acceleration performance of RDA for images of various sizes was evaluated through a simulator modified with gem5 and DRAMSim3 and achieved a 6.34–6.93× speedup and 41.9–48.2% energy savings.

This paper presents a quantitative design space exploration of fast Fourier transform (FFT) architectures and numerical formats for frequency-modulated continuous-wave (FMCW) radar processing on system-on-chip (SoC) platforms. Three hardware architectures were implemented and evaluated: a memory-based single-butterfly (SB) architecture, a pipelined single-path delay-feedback (SDF) architecture, and a parallel systolic-array (SA) architecture. Two numerical formats–32-bit fixed-point (FX32) and 16-bit half-precision floating-point (FP16)–were compared in terms of latency, throughput, accuracy, and hardware efficiency. Experimental results show that the SB architecture achieves the highest resource efficiency, processing 43.72 MFrame/s per LUT and 13.68 KFrame/s per DSP in FX32, and 37.60 MFrame/s per LUT and 35.10 KFrame/s per DSP in FP16. While FP16 slightly increases LUT utilization, it significantly enhances efficiency in DSP, FF, and BRAM resources, leading to more balanced hardware utilization overall. The SA architecture delivers the shortest latency and reducing range–Doppler-map (RDM) generation time by approximately 15.61% compared with SB, albeit at the cost of over 8.9× LUT and 6.5× DSP consumption. The SDF architecture achieves moderate throughput suitable for streaming but is constrained by memory bandwidth in SoC environments. From an architectural perspective, the SB design provides the best hardware efficiency, whereas from a numerical-format perspective, FP16 offers the most favorable trade-off between precision and resource usage. At the system level, increasing the AXI data width improved processing speed by 20–26%, while burst length tuning provided smaller gains of 4–5%. The results presented in this work provide practical design guidelines for implementing efficient FFT accelerators in SoC-based FMCW radar systems.

This paper presents a backprojection algorithm (BPA) accelerator implemented on a field-programmable gate array (FPGA) for circular synthetic aperture radar (SAR) systems. Although the BPA offers superior image quality, it requires significantly more computation and is memory intensive, necessitating hardware optimization. In particular, the BPA accumulates image data, leading to high memory requirements that must be reduced for embedded system implementation. To address this issue, we optimized the floating-point (FP) bit width, focusing on the output data that form the image, rather than only reducing the internal computation bit widths as in previous studies. Specifically, we optimized the exponent and mantissa widths in six computational units, prioritizing memory optimization for image data before reducing the computational logic. The proposed BPA accelerator achieved a 77% reduction in memory usage and a 73–74% reduction in computational logic while maintaining an image quality with a structural similarity index measure (SSIM) of 0.99 or higher. These optimizations significantly enhanced the feasibility of BPA processing in embedded systems.