The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this article, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range, and electrode dc offset (EDO) cancellation. An ac-coupled 1st-order digitally-intensive $\Delta $ - $\Delta \Sigma $ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits, and a digital control, has been fabricated in 22-nm fully depleted silicon on insulator (FDSOI) CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 $\mu \text{W}$ , and an input-referred noise of 7.7 ± 0.4 $\mu \text{V}_{\mathrm {rms}}$ in the AP band and 11.9 ± 1.1 $\mu \text{V}_{\mathrm {rms}}$ in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2nd-order hybrid-CTDT - modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional modulator, while employing an extra -stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18 μm CMOS process and achieves a peak SNR of 105.6dB and a dynamic range of 108.3dB, for a maximum input range of 720 mVpp. The measured input-referred noise is 0.98 Vrms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled $\Delta $ - $\Delta \Sigma $ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm ² per channel, an input-referred noise of 5.53 ± 0.36 $\mu \text{V}_{\mathrm{ rms}}$ in the action potential band and 2.88 ± 0.18 $\mu \text{V}_{\mathrm{ rms}}$ in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 $\text{M}\Omega $ . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

Voltage references (VRs) play a crucial role in the PMUs of electronic systems, providing a stable voltage regardless of process variations, supply voltage fluctuations, and temperature changes. The BGR has been widely employed as a reliable VR since the 1980s [1] , delivering approximately 1.2 V based on the silicon bandgap voltage ( V _BG ). However, designing a low-power and compact BGR presents challenges because of the power–area tradeoff [2] .

Spike sorting is a pivotal signal-processing technique used to extract information from raw extracellular recordings. Its performance is influenced by the characteristics of the neural recording front-end. This study explores how design choices in amplifiers, filters, and analog-to-digital converters (ADCs) affect the accuracy of well-established spike sorting algorithms. Our primary objective is to identify the minimal requirements that ensure high sorting accuracy while facilitating power- and area-efficient analog front-ends, which is especially needed for multi-channel recording-only applications. To achieve this, we use both synthetic and real datasets, serving as ground truth, processed through a generic MATLAB model of a neural recording front-end that simulates key electrical parameters impacting the signal integrity. These include the filter order and cutoff frequency, ADC resolution, ADC sampling frequency, and nonlinearity. Our findings indicate that optimal spike-sorting results are obtained with a 1st-order bandpass Butterworth filter ranging from 700 Hz to 7.5 kHz, coupled with an ADC that offers a 15-kHz sampling frequency at 8-bit resolution and no missing codes. These insights are crucial for designing high-channel-count neural interfaces where CMOS circuits must efficiently be optimized.

High-resolution ADCs require low noise and low distortion while consuming minimal power. This paper presents a power-efficient, calibration-free, 2nd-order noise-shaping (NS) SAR ADC. Mismatch error shaping (MES) is employed to reduce distortion from capacitive DAC mismatches. The resulting input range loss is compensated for by an additional digital prediction (DP) method. To mitigate the high power consumption of the multi-input dynamic comparator, this work proposes a coarse-fine comparison (CFC) scheme with an optimized error-correction capability, enabling the ADC to switch between SAR and NS-SAR modes. This approach reduces the power consumption of the comparator while maintaining NS functionality. Furthermore, to eliminate the need for an external high-speed clock to control SAR logic and NS operation, this work utilizes a fully asynchronous logic driven solely by a sample-and-hold clock. Implemented in standard 130-nm CMOS technology, this prototype ADC achieves a measured 81.54-dB SNDR (13.25-bit ENOB) in a 100-kHz bandwidth with an oversampling ratio (OSR) of 25.