To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 2.10 mm ) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μV in the action-potential band (300 Hz-10 kHz) and 5.4 μV in the local-field-potential band (1 Hz-300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.

We present a high electrode density and high channel count CMOS (complementary metal-oxide-semiconductor) active neural probe containing 1344 neuron sized recording pixels (20 µm × 20 µm) and 12 reference pixels (20 µm × 80 µm), densely packed on a 50 µm thick, 100 µm wide, and 8 mm long shank. The active electrodes or pixels consist of dedicated in-situ circuits for signal source amplification, which are directly located under each electrode. The probe supports the simultaneous recording of all 1356 electrodes with sufficient signal to noise ratio for typical neuroscience applications. For enhanced performance, further noise reduction can be achieved while using half of the electrodes (678). Both of these numbers considerably surpass the state-of-the art active neural probes in both electrode count and number of recording channels. The measured input referred noise in the action potential band is 12.4 µVrms, while using 678 electrodes, with just 3 µW power dissipation per pixel and 45 µW per read-out channel (including data transmission).

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this article, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range, and electrode dc offset (EDO) cancellation. An ac-coupled 1st-order digitally-intensive $\Delta $ - $\Delta \Sigma $ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits, and a digital control, has been fabricated in 22-nm fully depleted silicon on insulator (FDSOI) CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 $\mu \text{W}$ , and an input-referred noise of 7.7 ± 0.4 $\mu \text{V}_{\mathrm {rms}}$ in the AP band and 11.9 ± 1.1 $\mu \text{V}_{\mathrm {rms}}$ in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2nd-order hybrid-CTDT - modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional modulator, while employing an extra -stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18 μm CMOS process and achieves a peak SNR of 105.6dB and a dynamic range of 108.3dB, for a maximum input range of 720 mVpp. The measured input-referred noise is 0.98 Vrms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled $\Delta $ - $\Delta \Sigma $ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm ² per channel, an input-referred noise of 5.53 ± 0.36 $\mu \text{V}_{\mathrm{ rms}}$ in the action potential band and 2.88 ± 0.18 $\mu \text{V}_{\mathrm{ rms}}$ in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 $\text{M}\Omega $ . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

Fundamental neuroscience research and high-performance neuro-prostheses require large-scale brain interfaces with ever-greater spatial resolution across a large cortex coverage, which cannot be achieved with current passive (micro) electrocorticography (ECoG) technologies. In this article, we present an active micro-electrocorticography ( $\mu$ ECoG) implant system that circumvents these challenges while achieving significantly lower noise compared to other existing active $\mu$ ECoG arrays. The proposed brain implant system is composed of a flexible, actively multiplexed 256-electrode $\mu$ ECoG array and an incremental- $\Delta \Sigma$ readout integrated circuit (ROIC). The 1 cm $\times$ 1 cm $\mu$ ECoG array was fabricated in a 3- $\mu$ m IGZO thin-film transistor (TFT) technology on a 15- $\mu$ m flexible foil and coupled to a 1.25 mm $\times$ 1.25 mm CMOS ROIC fabricated in a 22-nm fully depleted silicon on insulator (FDSOI) process. Due to the 256:16 time-division multiplexing achieved in the electrode array, only 16 multiplexed channels are required in the ROIC to acquire signals from the 256 electrodes simultaneously. By combining TFT multiplexing with newly proposed bulk-DAC (BDAC) feedback in the readout channel, we can integrate and address 4 $\times$ more electrodes than other passive arrays, achieve $>$ 10 $\times$ less noise than existing active arrays, and obtain $>$ 2 $\times$ effective channel area reduction in the ROIC while maintaining comparable electrical performance over current state-of-the-art ( $\mu$ )ECoG readouts.