Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state ¹ switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multi-state memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multi-state memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

High-resolution ADCs require low noise and low distortion while consuming minimal power. This paper presents a power-efficient, calibration-free, 2nd-order noise-shaping (NS) SAR ADC. Mismatch error shaping (MES) is employed to reduce distortion from capacitive DAC mismatches. The resulting input range loss is compensated for by an additional digital prediction (DP) method. To mitigate the high power consumption of the multi-input dynamic comparator, this work proposes a coarse-fine comparison (CFC) scheme with an optimized error-correction capability, enabling the ADC to switch between SAR and NS-SAR modes. This approach reduces the power consumption of the comparator while maintaining NS functionality. Furthermore, to eliminate the need for an external high-speed clock to control SAR logic and NS operation, this work utilizes a fully asynchronous logic driven solely by a sample-and-hold clock. Implemented in standard 130-nm CMOS technology, this prototype ADC achieves a measured 81.54-dB SNDR (13.25-bit ENOB) in a 100-kHz bandwidth with an oversampling ratio (OSR) of 25.

Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm² while achieving input-referred noise levels of 6.26 and 3.54 µV_rms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mV_pp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces.

Ferroelectric-capacitor-based memory (FeRAM) is a promising emerging non-volatile memory technology that offers fast access and high endurance. Recent studies have demonstrated Ferroelectric-capacitor-based memory (FeRAM) has the potential to support Non-Destructive Readout (NDRO) as well as 3D stacking, enabling read operations that do not disturb or minor disturb the stored polarization state and higher density. However, variations in ferroelectric materials and layer structures lead to diverse hysteresis behaviors, resulting in different sensing requirements. In addition, the reduced capacitor size in deeply stacked 3D architectures further decreases the available charge, making accurate readout increasingly challenging. To better understand these issues, this work presents a highly scalable direct-capacitance-conversion characterization circuit that is capable of extracting the equivalent ferroelectric capacitance from a 3D FeRAM array. Leveraging a continuous-time delta-sigma modulator (CTDSM), the proposed platform can accurately quantize small ferroelectric equivalent capacitances ranging from 0 to 72fF with low noise and high resolution, and achieves a capacitance resolution of $0.045\mathrm {fF_{rms}}$ while consuming only $3\mu $ W power and occupying 0.001mm² chip area under a 22nm FDSOI technology. These results demonstrate the capability to characterize 3D FeRAM arrays with up to 64 vertically stacked ferroelectric capacitors (FeCAPs) and highlight strong scalability for large-scale FeRAM evaluation and design exploration.