In this paper, commercially 1200 V asymmetric and double trench silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (MOSFETs) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with MOSFET avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that the two failure mechanisms are identified, i.e. thermal runaway and gate oxide rupture. For asymmetric trench SiC MOSFETs, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC MOSFETs is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of DC parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.

In this paper, short-circuit capability prediction and failure mode of 1200 V-class SiC MOSFETs with double and asymmetric trench structure are proposed under single-pulse short circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various DC bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in short-circuit test. For asymmetric trench SiC MOSFETs, failure modes are gate damage at lower DC bus voltages and thermal runaway at higher DC bus voltages. Whereas failure mode for double trench SiC MOSFETs is thermal runaway at all various DC bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the DC bus voltage and peak short-circuit current of device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFETs by the post decapsulation.

In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and on -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of on -state resistance caused by thermal fatigue is observed.

novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge (Qgd) and gate-to-drain capacitance (Cgd) of LBD-MOSFET are significantly reduced by about 21W and 15W in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM1= Ron,sp×Qgd and HF-FOM2= Ron,sp×Cgd) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.

In this paper, an analytical switching loss model for Gallium Nitride (GaN) based control switch (CS) and synchronous rectifier (SR) in low-voltage buck converters is proposed. Based on the consideration of parasitic inductances, SR reverse conduction voltage drop, and overshoot current effect caused by output capacitance of SR, the total switching loss is modeled with regards to both CS and SR, which can lead to more accurate prediction of power loss and system efficiency in low-voltage buck converters. The modeling results show that the percentage of SR switching loss in total switching loss is 25.4% in the 12-1.2V converter, which is far larger than the 6.3% in the 48-5V converter, and this verifies the necessity of including SR into the model for low-voltage converters. Experiment results exhibit an average increase of 52.3 % and 66.1 % in accuracy of predicted system efficiency and converter power loss through proposed model with SR than conventional models from 400 kHz to 1 MHz.

A novel high performance SiC asymmetric cell trench MOSFET with split gate (SG) and integrated junction barrier schottky (JBS) diode (SGS-ATMOS) is proposed for the first time. The shielding effect provided by the SG structure not only reduces the gate-drain capacitance ( C _gd ) but also alleviates the electric field crowding in the dielectric layer at trench corner. The integrated trench JBS diode bypasses the PiN body diode while obtaining good double protection from the SG and p-type shielding region. Therefore, not only the MOSFET but also diode performance is significantly improved for the proposed structure. Numerical analysis results show that compared with the conventional asymmetric cell trench MOSFET (Con-ATMOS), the high frequency figure of merit (HFFOM ¹ , R _on · C _gd ) is reduced by 92.5% and the Baliga figure of merit (BFOM, BV ² /R _on,sp ) is increased by 57.2%, respectively. In addition, the forward conduction voltage drop ( V _F ), reverse recovery charge ( Q _rr ) and peak reverse recovery current ( I _rrm ) of the diode are reduced from 3.10V, 1.95μC/cm ² and 68.0A for the Con-ATMOS to 1.56V, 0.97μC/cm ² and 35.9A for the proposed SGS-ATMOS, respectively. Compared with the Con-ATMOS, the turn-on loss ( E _on ) and turn-off loss ( E _off ) of the proposed device are reduced by 33.3% and 33.0%, respectively. The E _on and E _off of the proposed device are also 33.6% and 30.0% off compared with the Con-ATMOS with external JBS diode, respectively. The temperature characteristics of the SGS-ATMOS are also discussed and it is found that the proposed device exhibits good performance at high temperature.