A silicon carbide (SiC) trench MOSFET (TMOS) with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investigated by simulation. The device features the integrated TLP-SBD that remarkably improves body diode characteristics while guarantees excellent fundamental performance of TMOS. In the blocking state, the P-base region, the trench gate, and the P+ shield at the trench bottom serve as the TLP of the Schottky contact. Each protection assists in depleting the drift region beneath Schottky contact. Benefiting from the self-assembled TLP, the leakage current of the integrated body diode of the ITS-TMOS is significantly reduced. Moreover, the reverse turn-on voltage (VON) and the gate charge (Qg) of the ITS-TMOS are 65% and 18% lower than those of the conventional TMOS, respectively. The improved overall performances make the SiC ITS-TMOS a competitive candidate for high-efficiency and high power density applications.

In this paper, commercially 1200 V asymmetric and double trench silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (MOSFETs) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with MOSFET avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that the two failure mechanisms are identified, i.e. thermal runaway and gate oxide rupture. For asymmetric trench SiC MOSFETs, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC MOSFETs is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of DC parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.

In this paper, short-circuit capability prediction and failure mode of 1200 V-class SiC MOSFETs with double and asymmetric trench structure are proposed under single-pulse short circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various DC bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in short-circuit test. For asymmetric trench SiC MOSFETs, failure modes are gate damage at lower DC bus voltages and thermal runaway at higher DC bus voltages. Whereas failure mode for double trench SiC MOSFETs is thermal runaway at all various DC bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the DC bus voltage and peak short-circuit current of device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFETs by the post decapsulation.

In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and on -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of on -state resistance caused by thermal fatigue is observed.

novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge (Qgd) and gate-to-drain capacitance (Cgd) of LBD-MOSFET are significantly reduced by about 21W and 15W in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM1= Ron,sp×Qgd and HF-FOM2= Ron,sp×Cgd) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.