In this paper, short-circuit capability prediction and failure mode of 1200 V-class SiC MOSFETs with double and asymmetric trench structure are proposed under single-pulse short circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various DC bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in short-circuit test. For asymmetric trench SiC MOSFETs, failure modes are gate damage at lower DC bus voltages and thermal runaway at higher DC bus voltages. Whereas failure mode for double trench SiC MOSFETs is thermal runaway at all various DC bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the DC bus voltage and peak short-circuit current of device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFETs by the post decapsulation.

In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and on -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of on -state resistance caused by thermal fatigue is observed.

In this letter, a novel planar gate SiC MOSFET with embedded auto-adjust normally-on JFET (ADJ-MOSFET) is proposed and characterized to improve short circuit capability. The normally-on auto-adjust JFET (AD-JFET) is embedded in P-well region as the conduction path of electrons from N-type source to the channel region of SiC MOSFET. Meanwhile, the P-type source of device splits into two parts, one of which serves as the gate of AD-JFET. Under high DC bus voltage (short circuit) conditions, the effective channel width of AD-JFET will be reduced by the increased depletion charge. Therefore, the potential barrier of AD-JFET channel will increase rapidly, making it difficult for electrons transporting. The potential barrier of AD-JFET will be adjusted by that of the JFET region in drift region automatically, resulting in a reduction of the saturation (peak short circuit) current caused by the higher potential barrier of SiC MOSFET. Compared with conventional planar gate SiC MOSFET, ADJ-MOSFET not only reduces 33% peak short circuit current, but also increases short circuit withstanding time from $8~\mu \text{s}$ to 14 $\mu \text{s}$ under 800 V DC bus voltage. Furthermore, an auto-adjust JFET barrier model is proposed for SiC ADJ-MOSFET.

A novel silicon carbide (SiC) asymmetric trench MOSFET with integrated low-loss diode (LLD-ATMOS) is proposed and investigated by numerical simulations to reduce switching loss and eliminate bipolar degradation of body diode. The N-channel region beneath the dummy gate provides a low barrier path to transport electrons form the N-drift layer to N+ source region, with the result that the forward conduction voltage drop is reduced from 3.5 V at 10 A of the pn body diode to 1.9 V at 10 A of the LLD-ATMOS. Furthermore, the reverse recovery charge (QRR) of LLD and the gate-to-drain capacitance ( ${C}_{\text {gd}}$ ) of LLD-ATMOS are 76% and 95% lower than those of the conventional asymmetric trench MOSFET (C-ATMOS). As a result, the turn-off and turn-on losses of LLD-ATMOS are reduced by 49% and 58%, respectively. The calculated high-frequency figure of merit ( $\text {HF-FOM} = {R}_{ {{\text{ON}}},\text {sp}} \times {C}_{\text {gd}}$ ) of LLD-ATMOS is tremendously decreased to one-fourteenth of the value of C-ATMOS. In addition, a conduction band energy analysis model for the LLD is developed. The improved performances suggest that LLD-ATMOS is a competitive option in power electronic systems.

A planar gate SiC MOSFET of hole extraction pillar combined with multilayer P-shield structure (HEMP-MOS) is proposed and characterized to improve single-event burnout (SEB) and single-event gate rupture (SEGR). The multiple P-shield layers are utilized to reduce the peak heat power caused by the strong electric field and high current at P-base/drift junction. Therefore, the maximum lattice temperature (hot spot) in HEMP-MOS is limited because of lower heat powers and larger areas of energy dissipation. The SEB threshold voltage of 850 V can be achieved with a linear energy transfer (LET) value of 77.9 MeV $\cdot $ cm2/mg for HEMP-MOS, which corresponds to an increase of 610 V for conventional SiC MOSFET and 140 V for SiC MOSFET with multilayer buffer. Moreover, when heavy ions strike near the center of the device, the hole extraction pillar provides an additional path to extract accumulated holes below the gate oxide induced by heavy ions, thus ameliorating electric field crowding in gate oxide and improving the SEGR performance. When heavy ions with an LET value of 77.9 MeV $\cdot $ cm2/mg strike the center of the device and the drain voltage is 50% rated voltage ( ${V}_{\text {DS}} = {600}$ V), the maximum gate oxide electric field in HEMP-MOS is as low as 2.3 MV/cm, which is one 27th of that in SiC MOSFET with multilayer buffer. These results show that HEMP-MOS provides a single-event effect (SEE) hardening structure for SiC MOSFET in aerospace applications.

Conventional planar- and trench-gate silicon carbide insulated-gate bipolar transistors (SiC C-IGBT and T-IGBT) suffer from higher turn- OFF loss ( ${E}_{\text {off}}$ ) and ON-state voltage drop [ ${V}_{\text {ce(sat)}}$ ]. An improved hybrid-channel injection enhanced modulation 4H-SiC IGBT (HC-IGBT) is proposed and investigated to overcome these shortcomings in this article. The proposed IGBT structure is considered 3-D because the gate wraps around a raised emitter-to-collector channel, instead of residing on top of the channel in the conventional 2-D planar-gate structure. Therefore, multiple gates are ganged together through the same gate electrode to enable more electrons in the “ON” state and provide more path to remove extra holes in the “OFF” state. Comparing with C-IGBT and T-IGBT structure, HC-IGBT gains an improvement of 108% and 21% in a differential specific ON-resistance as well as a turn- OFF loss reduction of 11% and 16%. The industrial figure of merit (IFOM $= {V}_{\text {ce(sat)}}\,\,\times \,\,{E}_{\text {off}}$ ) of HC-IGBT is reduced by 21% and 22% compared with C-IGBT and T-IGBT, respectively. Meanwhile, the Baliga’s figure of merit (BFOM $= {V}_{\text {BR}}^{{2}}/{R}_{\text {on,sp}}$ ) shows about 63% and 15% larger than that of C-IGBT and T-IGBT. These results show that HC-IGBT structure has much superior tradeoff between the ON-state voltage drop and turn- OFF loss, indicating the potential for ultrahigh-voltage power electronic of the future.