In this paper, we present an in-built N⁺ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at −0.7 V to induce a P⁺ region at the source side, leaving an N⁺ pocket between the source and the channel. This technique yields an N⁺ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N⁺ pocket yields a higher I_ON and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (E_C) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N⁺ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications.

A new structure for PNPN tunnel field-effect transistors (TFETs) has been designed and simulated in this work. The proposed structure incorporates the polarity bias concept and the gate work function engineering to improve the DC and analog/RF figures of merit. The proposed device consists of a control gate (CG) and a polarity gate (PG), where the PG uses a dual-material gate (DMG) structure and is biased at −0.7 V to induce a P⁺ region in the source. The PNPN structure introduces a local minimum on the conduction band edge curve at the tunneling junction, which dramatically reduces the tunneling width. Furthermore, we show that incorporating the DMG architecture further enhances the drive current and improves the subthreshold slope (SS) characteristics by introducing an additional electric field peak. The numerical simulation reveals that the electrically doped PNPN TFET using DMG improves the DC and analog/RF performances in comparison to a conventional single-material gate (SMG) device.

In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N⁺/P⁻ starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (L_gap), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10⁻¹⁶ A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical.