In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier lowering, improved intrinsic gain (A _V ), cutoff frequency (f _T ), and maximum oscillation frequency (f _MAX ). Our approach overcomes the difficulty of creating a narrow GC doping profile and, thus, makes the GC MOSFET more attractive in carrying on with the scaling trend. The possible fabrication process flow of GC-double-gate (DG) FET is also proposed.

In this paper, a 4H-SiC trench insulated gate bipolar transistor (IGBT) incorporating a Schottky contact in the collector side is proposed to reduce the turn-off energy loss. The proposed structure is explored and compared with the conventional IGBT using ATLAS. The simulation results have indicated that the reduction in turn-off energy loss is more than 88%, with a slight degradation in the I-V characteristics. Concurrently, with the same on-state voltage drop, the turn-off loss is reduced by a figure of 84%.

In this paper, we present an in-built N⁺ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at −0.7 V to induce a P⁺ region at the source side, leaving an N⁺ pocket between the source and the channel. This technique yields an N⁺ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N⁺ pocket yields a higher I_ON and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (E_C) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N⁺ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications.

A silicon-on-insulator-(SoI)-like bulk silicon (SL-BS) MOSFET structure is proposed and compared against an fully depleted SoI MOSFET using 2-D numerical simulations. The SL-BS MOSFET contains a p/n-/p structure, with n- is made of 4 H-SiC. This n- layer is fully depleted through the built-in potential of two p-n junctions. Simulations indicated that the proposed structure is better than SoI in short channel effects simulation except the threshold rolloff, and equivalent with SoI in single-event upset properties. The SL-BS MOSFET exhibits no significant self-heating effect. Overall, the simulation results indicated the proposed structure is suitable for replacing SoI technology for applications in environments with high-dose radiation.

In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 10¹² cm⁻². Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (I_d-V_g) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed.