Crystallographic characterization and the ferroelectric properties of 50 nm-thick sputter-deposited Al_0.78Sc_0.22N films deposited at room temperature (RT) and 400 °C are investigated. c-axis oriented growths were confirmed by x-ray diffraction patterns with rocking curve measurements for both samples. Al_0.78Sc_0.22N films were found to grow in the c-axis direction and showed poling-free ferroelectric properties, which are advantageous for practical memory and piezoelectric applications. Although the metal-ferroelectric-metal (MFM) capacitors represent low switching cycle endurance, MFM capacitors revealed remnant polarization (P_r) of 70 μC/cm² and 113 μC/cm² for RT- and 400 °C-deposited samples, respectively. Ferroelectric films with low-temperature process capability can open a wide range of applications.

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.

When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the interface bonding structures of the tungsten/lanthanum oxide/silicon (W/La2O3/Si) MOS structure. We found that both W/La2O3 and La2O3/Si are thermally unstable. Thermal annealing can lead to W oxidation and the forming of a complex oxide layer at the W/La2O3 interface. For the La2O3/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers do not only cause significant device performance degradation, but also impose a limit on the thinnest equivalent oxide thickness (EOT) to be achievable which may be well above the requirements of our future technology nodes.

This letter reports an E-mode GaN MIS-HEMT using a composite La ₂ O ₃ /HfO ₂ gate insulator for power device applications. The composite dielectric formed an amorphous LaHfOx layer after post-deposition annealing. The GaN MIS-HEMT with amorphous LaHfOx gate dielectric showed good oxide film quality and excellent HfLaOx/GaN interface properties, as demonstrated by the measured C-V characteristics. Consequently, the E-mode MIS-HEMT was determined to show good V _th stability with only a slight increase in the dynamic R _on after high drain bias stress.