With the development of Moore's Law, the design complexity of SoC is increasing, and the traditional simulation verification method has been unable to meet the rapid iteration of products. A high-performance SoC simulation model design scheme based on Verilator is proposed to improve the speed of SoC simulation verification and shorten the chip development and design cycle. Based on the ESL design method, Openc910 is selected as the starting point to design a high-performance SoC simulation model based on Verilator. The SM3 and SM4 crypto modules are designed in the SoC, and Iverilog simulation tool is used for comparison. Compared with using the traditional Iverilog simulation, the experimental results using Verilator show the effectiveness of the design.

This study proposes a hysteretic current mode step‐up DC–DC converter with ultra‐low startup voltage, low output ripple and high efficiency, which is suitable to be used as a power supply for an accurately voltage controlled systems, high‐efficiency devices and low‐voltage supply applications. A startup module is used for operating the switches when the input voltage is not high enough to supply the control circuit. The output ripple is restricted by a fixed‐hysteretic current mode controller whether the load is heavy or light. The high efficiency is obtained by applying an auto‐mode changed technology under light load. This makes some sub‐circuits of the chip enter into the power save mode and shuts down the power switching devices. At the same time, a back‐gate diode of the rectifying power metal‐oxide semiconductor device is used for maintaining output voltage. The chip has been made with a standard 0.35‐μm complementary metal‐oxide semiconductor process forming an area of only 960 μm × 820 μm. Experimental results show that the minimum startup voltage is 0.8 V; and the output voltage ripple is <10 mV. Moreover, the peak efficiency is 95% with a heavy load that can prolong battery life.

In this paper, a new wideband circularly polarized (CP) antenna with a single-layer metasurface (MT) is developed. The single-layer MT consists of 4 × 4 truncated corner square patch cells with corner-cut square slots. Compared to the single truncated corner square patch, introducing corner-cut square slot can increase the design flexibility by changing the slot size for a wider CP operating bandwidth. A slit-shaped aperture coupling structure and a microstrip fed structure are placed together to provide coupling energy to the MT. Note that such MT and slot antenna share the same reference ground plane, and there is no air gap among the overall CP antenna structure. This design could easily make the profile low and the structure compact. The tested results reveal that the presented antenna features a broad 3-dB axial ratio bandwidth (18.2%, 5.25 ~ 6.3 GHz) and a wide −10-dB impedance bandwidth (19%, 5.25 ~ 6.35 GHz), which is very suitable for wireless communication systems with low-profile and wideband requirements.

A novel current‐sensing technique with fast transient and high accuracy for a step‐up DC–DC converter is presented. This circuitry is applied for sensing the current flowing through the equivalent series resistor (ESR) of the inductor to obtain the inductor current information. It is achieved with a fast transient response circuit (FTRC), an operational amplifier, a current‐sensing stage and an overshoot current protection circuit. The process offsets of the transistors, which can increase the current‐sensing accuracy, and provide an additional current feedback loop to decrease the transient response time are compensated by the FTRC. When the sensed current is higher than the maximum value, the overcurrent protection (OCP) will be operating to let it shut down. This current‐sensing technique has been integrated in a step‐up DC–DC converter with standard 0.35 μm CMOS process. Experimental results show that the accuracy is higher than 98% and the transient response recovery time is ∼100 μs with load current changing from 3 A to 10 mA.

The Prognostic and Health Management (PHM) technology has been widely used as means of improvement for reliability, safety and availability of new generation weapons and commercial products, achieving autonomic logistics. In avionics system, European countries and the USA have been promoting the development, maturing of PHM critical technologies and their applications in military and commercial aircrafts. PHM application and design ideas in avionics system are analyzed, functional relations of PHM system and architecture of health management system suitable for integrated avionics system are proposed. In order to improve the prognostic ability of the avionic data processing modules, some ageing test has been done, but it will take a long time to degenerate the components and modules to the critical point, varies fault injection ways are introduced in the paper. The novel way can calculate the life expectancy by combining the failure physics modules, reduce the ageing test workload, which is significant to life prediction. So, this PHM system can play a very important role in avionics data processing modules.