In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by 4.0 x (2.7 x) and 1.8 x (2.1 x) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) on-state current enhancement in 3-nm node n-(p-)FinFETs.

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

Along with the increasing integration of renewable energy generation in AC-DC power networks, investigating the dynamic behaviors of this complex system with a proper equivalent model is significant. This paper presents an equivalent modeling method for the AC-DC power networks with doubly-fed induction generator (DFIG) based wind farms to decrease the simulation scale and computational burden. For the AC-DC power networks, the equivalent modeling strategy in accordance with the physical structure simplification is stated. Regarding the DFIG-based wind farms, the equivalent modeling based on the sequential identification of multi-machine parameters using the improved chaotic cuckoo search algorithm (ICCSA) is conducted. In light of the MATLAB simulation platform, a two-zone four-DC interconnected power grid with wind farms is built to check the efficacy of the proposed equivalent modeling method. From the simulation analyses and comparative validation in different algorithms and cases, the proposed method can precisely reflect the steady and dynamic performance of the demonstrated system under N-1 and N-2 fault scenarios, and it can efficiently achieve the parameter identification of the wind farms and fulfill the equivalent modeling. Consequently, the proposed approach’s effectiveness and suitability are confirmed.