In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by 4.0 x (2.7 x) and 1.8 x (2.1 x) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) on-state current enhancement in 3-nm node n-(p-)FinFETs.

This work proposes Total Ionizing Dose (TID) hardening techniques compatible with conventional 14-nm-node silicon-on-insulator (SOI) FinFETsf process flows through performing 3-dimensional (3-D) simulations based on technology computer-aided design (TCAD) tools. The simulation results reveal a significantly critical TID impact induced by trapped charges in the buried oxide (BOX) and the spacer with calibration against 14 nm SOI FinFETfs experimental data (error < 6%). Inspired by the physical interpretation, an optimization technique featuring an optimized gate structure, spacer length, and substrate bias is designed. The optimized gate structure is utilized to enhance the local gate-to-channel coupling at the bottom and reduce the generation and capture of electron-hole pairs. By reducing the spacer length, a lower sensitive volume in the spacer can effectively suppress the TID response. The setting of the negative substrate bias greatly improves the subthreshold characteristics, weakening the TID effect in the BOX. By adopting the combined optimization including these techniques, the threshold voltage shift (VTH) induced by a 5 Mrad(SiO2) irradiation can be reduced to 21 mV, whereas VTH is 45 mV with only gate structure optimized and 97 mV without hardening. Meanwhile, the ION/IOFF after radiation increases to 1 × 107, which is at least four orders of magnitude better than the original device. Meanwhile, subthreshold swing (SS) is reduced from 81 mV/dec to 71 mV/dec, and Drain Induced Barrier Lowering (DIBL) is reduced from 120 mV/V to 99 mV/V, respectively. The combined optimization design is demonstrated as an effective method to improve the tolerance against TID irradiation without compromising performance, promoting 14 nm SOI FinFET’s application in future harsh space environments.

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

Radiation effects of a 150 keV proton beam with various fluences on GaN-based quasi-vertical p–i–n diodes are investigated. For fundamental analysis, the electrical properties of P-GaN and N⁻-GaN separated from p–i–n diodes are also investigated. With the increase in the radiation-induced defect (e.g., V_N and V_Ga) density, the carrier concentrations and mobilities of P-GaN and N⁻-GaN decrease significantly. Under the proton fluence of 1 × 10¹⁵ p/cm², P-GaN has been transformed into highly resistive N-GaN, resulting in p–i–n diodes losing electrical characteristics of the PN junction. Meanwhile, the P-GaN Ohmic contact has been converted to Schottky contact. In addition, due to a large number of radiation-induced defects in P-GaN and N⁻-GaN, the reverse leakage current mechanism is revealed to change from space-charge-limited current conduction to Ohmic conduction.

Recent studies on carbon nanotube (CNT) field-effect transistors (FETs) and integrated circuits (ICs) have shown their potential in radiation tolerance. However, most studies have focused on the displacement damage (DD) effect and total ionizing dose (TID) effect, while the single event effect (SEE) remains insufficiently explored. In this work, we thoroughly examined the SEE of the CNT devices. Using a pulse laser as the irradiation source, the CNT FETs and static random-access memory (SRAM) exhibited an excellent radiation tolerance with a laser threshold energy of 5 nJ/pulse for SEE. Additionally, we used technology computer-aided design (TCAD) tools to explore SEE mechanisms of the CNT-based electronics. Owing to the nanoscale cross-sections and the special SEE mechanism in CNT, the CNT FETs and SRAMs presents higher SEE tolerance compared to the Si-based devices, meaning that CNT based ICs are an excellent technology for the applications of outer space exploration.