The existence of buried oxide (BOX) layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully depleted silicon-on-insulator (FDSOI) device. To mitigate the radiation impact, a new structure named double SOI is introduced in this paper. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the BOX layer. With this structure, FDSOI device parameter degradation due to total dose is studied, and some abnormal phenomena, such as the transconductance hump and the mobility enhancement, are observed and discussed. Sentaurus TCAD simulations are used for further analysis. Moreover, the impact of negative back-gate bias to transistor parameter degradation is investigated, and an improved back-gate compensation strategy is proposed. Technology improvement such as thinning the BOX on total ionizing dose (TID) amelioration is also discussed with TCAD simulation.

The total ionizing dose response of bulk nFinFETs with multiple gate lengths and multiple fins is investigated for on-state bias condition. Experiments and Technology Computer Aided Design simulations were performed to analyze the effect of the trapped charges in the gate oxide and shallow trench isolation (STI) oxide on the threshold voltage and transconductance of the devices. The increases in the threshold voltage and transconductance are observed after X-ray irradiation. The positive shift of the threshold voltage is caused by the net negative charges trapped in the gate oxide. The simulation results show that the trapped holes in the STI oxide reduce the electric field and increase the electron mobility in channel near the fin bottom, which is the major contribution to the increased transconductance. An interesting phenomenon was also observed that the threshold voltage continues to increase during the annealing process, whereas the transconductance decreases. These results suggest that there may also be a small amount of trapped holes in gate oxide during irradiation, and those trapped holes are compensated by electrons transporting from the silicon during the anneal, leading to further positive shift of the threshold voltage. Moreover, the decrease in transconductance is mainly introduced by the neutralization of the trapped holes at STI/silicon interface.

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat.

Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxide-nitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs.