InSnO (ITO) thin-film transistors (TFTs) attract much attention in fields of displays and low-cost integrated circuits (IC). In the present work, we demonstrate the high-performance, robust ITO TFTs that fabricated at process temperature no higher than 100 °C. The influences of channel thickness (t_ITO, respectively, 6, 9, 12, and 15 nm) on device performance and positive bias stress (PBS) stability of the ITO TFTs are examined. We found that content of oxygen defects positively correlates with t_ITO, leading to increases of both trap states as well as carrier concentration and synthetically determining electrical properties of the ITO TFTs. Interestingly, the ITO TFTs with a t_ITO of 9 nm exhibit the best performance and PBS stability, and typical electrical properties include a field-effect mobility (µ_FE) of 37.69 cm²/Vs, a V_on of −2.3 V, a SS of 167.49 mV/decade, and an on–off current ratio over 10⁷. This work paves the way for practical application of the ITO TFTs.

Transparent electrodes are a core component for transparent electron devices, photoelectric devices, and advanced displays. In this work, we fabricate fully-transparent, highly-conductive Al-doped ZnO (AZO) films using an atomic layer deposition (ALD) system method of repeatedly stacking ZnO and Al₂O₃ layers. The influences of Al cycle ratio (0, 2, 3, and 4%) on optical property, conductivity, crystallinity, surface morphology, and material components of the AZO films are examined, and current conduction mechanisms of the AZO films are analyzed. We found that Al doping increases electron concentration and optical bandgap width, allowing the AZO films to excellently combine low resistivity with high transmittance. Besides, Al doping induces preferred-growth-orientation transition from (002) to (100), which improves surface property and enhances current conduction across the AZO films. Interestingly, the AZO films with an Al cycle ratio of 3% show preferable film properties. Transparent ZnO thin film transistors (TFTs) with AZO electrodes are fabricated, and the ZnO TFTs exhibit superior transparency and high performance. This work accelerates the practical application of the ALD process in fabricating transparent electrodes.

In the present work, we testify a strategy to achieve high-performance ZnO thin film transistors (TFTs) on a flexible PET substrate at a maximum process temperature no more than 100 ∘C. Interestingly, the ZnO TFTs exhibit superior electrical properties, including a field-effect mobility of 14.32 cm2V-1s-1, a sub-threshold swing of 0.21 V/decade, and an on-to-off current ratio of 3.03×107. Also, ideal uniformity, hysteresis property, contact resistance, and stability are achieved. Threshold voltage shift (ΔVTH) under positive and negative bias stress are 0.17 and –0.18 V, respectively. Moreover, the ZnO TFTs manifest good mechanical performance at a bending radius of 10 mm. We expect that our findings propel practical application of the oxide TFTs in flexible electronics.

This letter demonstrates bi-layer channel Al-doped ZnO/ZnO thin film transistors (AZO/ZnO TFTs) via atomic layer deposition process at a relatively low temperature. The effects of annealing in oxygen atmosphere at different temperatures have also been investigated. The ALD bi-layer channel AZO/ZnO TFTs annealed in dry O2 at 300 °C exhibit a low leakage current of 2.5 × 10−13A, I on/I off ratio of 1.4 × 107, subthreshold swing (SS) of 0.23 V/decade, and high transmittance. The enhanced performance obtained from the bi-layer channel AZO/ZnO TFT devices is explained by the inserted AZO front channel layer playing the role of the mobility booster.

The resistivity of Cu interconnects increases rapidly with continuously scaling down due to scatterings, causing a major challenge for future nodes in M0 and M1 layers. Here, A Boltzmann-transport-equation-based Monte Carlo simulator, including all the major scattering mechanisms of interconnects, is developed for the evaluation of electron transport behaviors. Good agreements between our simulation and the experimental results are achieved for Cu, Ru, Co, and W, from bulk down to 10 nm interconnects. The line resistance values of the four materials with the inclusion of liner and barrier thicknesses are calculated in the same footprint for a fair comparison. The impact of high aspect ratio on resistivity is analyzed for promising buried power rail materials, such as Ru and W. Our results show that grain boundary scattering plays the most important role in nano-scale interconnects, followed by surface roughness and plasma excimer scattering. Surface roughness scattering is the origin of the resistivity decrease for high-aspect-ratio conductive rails. In addition, the grain sizes for the technical nodes of different materials are extracted and the impact of grain size on resistivity is analyzed.